Motorola Corporation

Semiconductor Components Industries, LLC

Ira E Baskett

Andrew C McNeil

Cleon Petty

Lynn William Ford

Ronald C Pennell

Brian D Meyer

Gene T Sluss

George B Gritt, Jr

In one embodiment, a fan out buffer has the inputs of a plurality of output followers connected to the output of a plurality of distribution gates.

Fan out buffer and method therefor

In one embodiment, a delay circuit is formed to use cascode coupled transistors to receive signals from a differential pair and increase the propagation through the delay circuit.

Delay circuit and method therefor

In one embodiment, a differential transistor pair of an ECL differential amplifier is formed on two different semiconductor die.

Interface system and method therefor

In one embodiment, a pair of differential amplifiers have outputs coupled together. A signal received on one input results in signals coupled to the outputs that substantially cancel each other at the outputs.

Cross-talk reduction circuit and method therefor

In one embodiment, an ECL logic device uses a capacitor to couple a positive voltage to an output and reduce the rise time of the output signal.

High slew ECL device and method therefor

In one embodiment, a differential amplifier uses a diode coupled transistor and a series resistor to set a Voh output level and uses another transistor in parallel with the diode coupled transistor and resistor to set a Vol output level.

Method of forming a wide bandwidth differential amplifier and structure therefor

A reference voltage generator () is formed to include a bipolar current mirror the forms an output current () that is a function of a Vbe voltage of a reference transistor () and the difference between the Vbe voltage of the reference transistor () and a difference transistor ().

Method of forming a reference voltage generator and structure therefor

A differential logic gate (,) is provided with three current sources (,and,). Current source (,) provides keep alive current flowing through transistor (,) when a logic low is presented at the base terminal of transistor,. Current source (,) provides keep alive current flowing through transistor (,) when a logic low is presented at the base terminal of transistor,. Current source (,) provides additional current drive when either transistor (,) or transistor (,) is conducting maximum current. Keep alive current sources (,and,) allow operation of differential logic gate (,) at reduced peak to peak voltage transitions with reduced ringing and smoother logic transitions.

Differential logic circuit and method of use

A circuit and method for correcting a sense signal of a sensor (,) where the sense signal is reduced by a negative nonlinear error component introduced by membrane stress in a sensor structure (,). A first transducer (,) is disposed at a location (,) having substantial bending stress to produce a sense signal having a linear component and the nonlinear error component. A second transducer (,) is disposed at a location (,) with substantially zero bending stress to produce a sense signal having the nonlinear error component but a substantially zero linear component. The sense signal from the second transducer (,) is added to the sense signal from the first transducer (,) to correct the nonlinear error for producing a linear output sense signal (V,) of the sensor (,) which is representative of the physical condition.

Circuit and method of compensating for membrane stress in a sensor

A piezoresistive pressure sensor (30) has four resistive diffused regions (32) coupled into a bridge configuration (33) with four junctions (36) and four inside corners (40). Each of the diffused regions has a first end connected to one of the four junctions and a second end connected to a different one of the four junctions. There are four contact diffusion terminals (34) disposed in contact with the bridge configuration, and each of the diffusion terminals is disposed at one of the four junctions such that the diffused regions are electrically connected essentially only by the contact diffusion terminals and an overlap (44, 46) is provided between each of the diffusion terminals and the inside corners to accommodate mask misalignment during manufacture. Thus, no tap is required to electrically connect the contact diffusion terminals to the resistive diffused regions of the bridge, which results in increased sensor sensitivity.

Piezoresistive sensor bridge having overlapping diffused regions to

A compensation circuit (106) corrects for nonlinearities in a sensor signal representing the physical state of a sensor (100). A transducer (102) produces a non-linear component in a transducer voltage signal. A voltage-current converter (104) converts the tranducer voltage signal to a transducer current which contains the non-linear component. A compensation circuit (106) squares the transducer current (I.sub.216) and uses a scaling current (I.sub.412) to generate a compensation current (I.sub.408) equal to the non-linear component. The current (I.sub.216) and scaled compensation current (I.sub.408) are summed at a summing junction (418) to produce an output current (I.sub.OUT) which is a substantially linear representation of the physical state of the sensor.

Circuit and method of compensating for non-linearities in a sensor signal

An edge die bond semiconductor package including a semiconductor die having an active major surface and a mounting edge substantially orthogonal to the active surface, a base having a mounting surface, and material affixing the mounting edge of the semiconductor die to the mounting surface of the base.

Edge die bond semiconductor package

A method for setting the sensing polarity of a sensor device (10) uses a switching bridge (22) having a wheatstone bridge configuration that is coupled to a sensing element (20) such that the polarity of the sensor device can be set by creating two electrical opens, for example with laser trimming along a cut line (59, 66), in parallel branches (30, 31) of the switching bridge. These opens are formed after the sensor device has been fully processed.

Method for setting sensing polarity of a sensor device

A method of etching a semiconductor wafer includes providing a wafer having a portion thereof to be etched. A highly doped region is formed in the periphery of the wafer which is subsequently etched. The highly doped region of the wafer is substantially etch resistant to an etchant relative to the portion of the wafer being etched.

Wafer etch protection method

A stress isolating signal path having one end of fixed to a bonding pad of an integrated circuit chip and another end which forms a flexible bonding surface is provided. The flexible bonding surface may be bonded to external package components or external circuitry using conventional wire bond, epoxy bond, tape automated bonding, flip chip bonding, or the like. The signal path is formed using conventional semiconductor thin film deposition, patterning, and etching techniques. The signal path comprises a conductive material compatible with batch semiconductor manufacturing technology.

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Tempe, AZ, United States of America

Ira E Baskett