Texas Instruments Corporation

International Business Machines Corporation

Iqbal Ali

Amitava Chatterjee

Wei William Lee

Maureen A Hanratty

Greg A Hames

Qizhi He

Quzhi He

Theodore Warren Houston

Somnath S Nag

Keith Alan Joyner

Jeffrey A McKee

Ih-Chin Chen

Gregory Boyd Shinn

Srini Raghavan

Yin Hu

Peter S McAnally

Sudipto Ranendra Roy

Rajani C Shah

Shelley H Peterman

Agerico L Esquirel

A gate structure which includes a semiconductor substrate having a channel region, a gate insulator adjacent the channel region of the semiconductor substrate and a conductible gate adjacent the gate insulator. A primary insulation layer is adjacent the semiconductor substrate, the primary insulation layer having an opening where the gate insulator contacts the semiconductor substrate and an isolation dielectric layer adjacent the primary insulation layer, the isolation dielectric layer having an opening where the conductible gate is located and the isolation dielectric layer having a silicon oxynitride material.

Transistor having improved gate structure

A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer ( ) may be formed adjacent a substrate ( ). A disposable gate ( ) may be formed adjacent the primary insulation layer ( ). An isolation dielectric layer ( ) may be formed adjacent the primary insulation layer ( ). The disposable gate ( ) may be removed to expose a portion of the primary insulation layer ( ). The exposed portion of the primary insulation layer ( ) may be removed to expose a portion of the substrate ( ). The primary insulation layer ( ) may be selectively removable relative to the isolation dielectric layer ( ). A gate insulator ( ) may be formed on the exposed portion of the substrate ( ). A gate ( ) may be formed adjacent the gate insulator ( ).

Transistor having an improved gate structure and method of construction

A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (,) having a channel region (,). A gate insulation (,) may be adjacent the channel region (,) of the semiconductor substrate (,). A gate (,) may be formed adjacent the gate insulation (,). A sidewall insulation body (,) may be formed adjacent a portion of the gate (,). The sidewall insulation body (,) is comprised of a silicon oxynitride material. An epitaxial layer (,) may be formed adjacent a portion of the sidewall insulation body (,) and adjacent the semiconductor substrate (,) substantially outward of the channel region (,). A buffer layer (,) may be formed adjacent a portion of the sidewall insulation body (,) and adjacent the epitaxial layer (,).

Transistor having an improved sidewall gate structure and method of construction

A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

Method of forming a transistor having an improved sidewall gate structure

A post chemical-mechanical polishing clean-up process. Particles and ionic and metallic contaminants remaining on wafer 32 surface after CMP are removed and scratches are smoothed. The wafer 32 may be subjected to a high pressure/high rotational speed rinse at spindle rinse station 42 followed by buffing of the wafer 32 on a second polishing platen 38. If desired, a second high pressure/high speed rinse at spindle rinse station 42 may be performed after the buffing step. The wafer 32 may then be then transferred to a tank 50 for a megasonic bath and after the megasonic bath, the wafer 32 is transferred to a scrubber 44, which scrubs both surfaces of the wafer 32 with brushes and then spins the wafer 32 dry as spin station 84. All transfers are performed in a solution such as DI water to prevent drying of slurry on the wafer surface.

Post-chemical mechanical planarization clean-up process using

A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to 'dishing' that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

Reducing non-uniformity in a refill layer thickness for a semiconductor

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Iqbal Ali