Sandisk Technologies Inc.

Ippei Yasuda

Masaaki Higashitani

Ken Oowada

Kiyohiko Sakakibara

Adarsh Rajashekhar

Zhixin Cui

Keigo Kitazawa

A method of forming a three-dimensional memory device includes forming an alternating stack of in-process composite layers and sacrificial material layers including a lower insulating layer, a sacrificial spacer layer including silicon nitride or a semiconductor material, and an upper insulating layer, forming a memory opening vertically extending through the vertical stack, forming a memory opening fill structure in the memory opening, the memory opening fill structure including an in-process memory film and a vertical semiconductor channel, forming backside trenches through the alternating stack, replacing the sacrificial material layers with electrically conductive layers by removing the sacrificial material layers to form backside recesses and by depositing an electrically conductive material in the backside recesses, and converting the in-process composite layers into composite insulating layers by removing the sacrificial spacer layers to form lateral cavities and by optionally depositing replacement dielectric material layers in the lateral cavities.

Three-dimensional memory device including discrete memory elements and method of making the same

Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

Boosting read scheme with back-gate bias

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.

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Mie, Japan

Ippei Yasuda