Xilinx, Inc.

Ionut C Cical

Edward Cullen

John K Jennings

Diarmuid Collins

Chandrika Durbha

Christophe Erdmann

Umanath R Kamath

Brendan Farley

Bob W Verbruggen

Darragh Walsh

April M Graham

Ivan Bogue

A low current line termination circuit includes first and second input interfaces each configured to receive a Vreceive+ and a Vreceive&#x2212; voltage, respectively. The circuit further includes a first diode connected transistor ('DCT') coupled to the second input interface, a first switching transistor ('ST') coupled to the first DCT and to the first input interface, and a first delay element coupled between one of the input interfaces and a gate of the first ST. The circuit further includes a second DCT coupled to the one of the two input interfaces, a second ST coupled to the second DCT and to the second input interface, and a second delay element coupled between another of the two input interfaces and a gate of the second ST.

Low current line termination structure

Examples described herein provide an apparatus having a circuit with a grounding circuit and a switch. The apparatus generally includes a gate induced drain leakage (GIDL) protection circuit coupled to the switch and to an output voltage. The GIDL protection circuit may include a switch protection circuit configured to maintain a drain voltage of the switch less than a first supply voltage (V) when the circuit is in an OFF state; and a ground protection circuit configured to maintain a drain voltage of the grounding circuit less than the first supply voltage when the circuit is in an ON state.

Gate induced drain leakage robust bootstrapped switch

A temperature sensor includes a current source to produce a first bias current and a second bias current, a plurality of diodes, and temperature estimation circuitry. The plurality of diodes includes at least a first diode to receive the first bias current and a second diode to receive the second bias current. The temperature estimate circuitry measures a first voltage bias across the first diode resulting from the first bias current and a second voltage bias across the second diode resulting from the second bias current, and estimates a temperature of an environment of the temperature sensor based at least in part on the first voltage bias and the second voltage bias. The temperature sensor further includes error detection circuitry to measure at least one of the first or second bias currents and determine an amount of error in the temperature estimate based at least in part on the measurement.

Bias current variation correction for complementary metal-oxide-semiconductor (CMOS) temperature sensor

Examples described herein provide for a relaxation oscillator and corresponding methods of operation. In an example, a circuit includes a dynamically controllable current source, a capacitor, and an oscillator generation circuit. The dynamically controllable current source includes a digitally tunable current mirror configured to generate a current. The digitally tunable current mirror includes multiple transistors configured to be selectively electrically connected in parallel to alter a gain of the digitally tunable current mirror to control the current. The capacitor is selectively electrically connected to the dynamically controllable current source. The oscillator generation circuit is electrically connected to the capacitor. The oscillator generation circuit is configured to generate an oscillation signal in response to a voltage of the capacitor.

Relaxation oscillator having a dynamically controllable current source

A complementary metal-oxide-semiconductor (CMOS) switching system with increased supply rejection is disclosed. The system comprises a voltage regulator and a CMOS circuit. The voltage regulator receives a supply voltage and generates a regulated voltage by regulating an amplitude of the received supply voltage. The CMOS circuit includes an input terminal to receive a first voltage, switching circuitry to selectively couple the CMOS circuit to the voltage regulator in one of a plurality of configurations, and an output terminal to output a second voltage based at least in part on the first voltage and the regulated voltage when the CMOS circuit is coupled to the voltage regulator in a first configuration of the plurality of configurations.

Method of increased supply rejection on single-ended complementary metal-oxide-semiconductor (CMOS) switches

A voltage divider is described. The voltage divider comprises a pair of input nodes for receiving an input signal; a pair of output nodes configured to generate an output signal; a first capacitor having a first terminal coupled to a first output node of the pair of output nodes and a second terminal coupled to a second output node of the pair of output nodes; and a second capacitor having first terminal and a second terminal; a bypass switch having a first terminal coupled to the first terminal of the second capacitor and a second terminal coupled to the second terminal of the second capacitor; and a charge sharing switch coupled to the second terminal of the second capacitor; wherein the bypass switch and the charge sharing switch enable the sharing of charge between the first capacitor and the second capacitor.

Voltage divider and method of implementing a voltage divider

A circuit for extending the bandwidth of a termination block is described. The circuit comprises an I/O contact configured to receive an input signal; and a termination circuit coupled to the I/O contact, wherein the termination circuit comprises a plurality of trim legs coupled between a power supply and the I/O contact, each trim leg having a switch to control the impedance in the trim leg.

Circuit for and method of extending the bandwidth of a termination block

An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to-temperature current.

Programmable temperature coefficient analog second-order curvature compensated voltage reference

A device may include a voltage-to-current converter circuit having an operational transconductance amplifier (OTA), the voltage-to-current converter circuit for generating a bias current that is proportional to a reference voltage at a reference voltage input port of the OTA, and a bias current feedback path for providing the bias current to a bias current input port of the OTA. The device may further include a startup current generator circuit coupled to the bias current input port of the OTA, the startup current generator circuit controllable to provide a startup current to the bias current input port during a startup of the device and to be deactivated after the startup of the device.

Self-biased operational transconductance amplifier-based reference circuit

In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage. A control circuit is coupled to the analog switch to provide the modulated N-channel and modulated P-channel gate voltages each of which alternates between a respective supply voltage and a respective gate induced drain leakage (GIDL) mitigation voltage based on the switch state.

Analog switch having reduced gate-induced drain leakage

A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.

Circuit for and method of receiving an input signal

Various example implementations are directed to circuits and methods for generating a clock signal. According to an example embodiment, a circuit arrangement includes a relaxation oscillator configured to output a clock signal. The clock signal has an oscillation frequency dependent on a reference current provided to the relaxation oscillator, an operating temperature of the relaxation oscillator, and a supply voltage used to power the relaxation oscillator. The circuit arrangement also includes a current source coupled to the relaxation oscillator and configured to generate the reference current. The current source is configured to adjust the reference current, in response to a change in one or more of the temperature of the relaxation oscillator and the supply voltage, to inhibit change in the oscillation frequency of the clock signal.

Relaxation oscillator

In an example, a temperature-corrected voltage reference circuit for use in an integrated circuit (IC) includes a voltage reference circuit, a programmable gain amplifier, and a digital control circuit. The programmable gain amplifier includes a first input coupled to the voltage reference circuit, a second input coupled to receive a control signal, and an output coupled to provide a temperature-corrected voltage reference. The digital control circuit includes an input coupled to receive a temperature signal indicative of temperature of the IC and an output coupled to the second input of the programmable gain amplifier, the digital control circuit generating the control signal in response to the temperature signal.

Temperature correction of an on-chip voltage reference

Devices for isolating an input from an output are disclosed. For example, a device includes a first p-type metal oxide semiconductor transistor and a first circuit. A source of the first p-type metal oxide semiconductor transistor is connected to an input of the device. The first circuit is for delivering a signal on the input of the device to a gate of the first p-type metal oxide semiconductor transistor when an enable signal is deactivated and for delivering a ground voltage to the gate of the first p-type metal oxide semiconductor transistor when the enable signal is activated.

Switch supporting voltages greater than supply

A circuit for implementing a charge/discharge switch in an integrated circuit is described. The circuit comprises a supply bias path coupled to a first node, wherein the supply bias path provides a charging bias current to the first node; a charge transistor connected between the first node and a first terminal of a capacitor; a charge switch coupled between the first node and a ground potential, wherein the charge switch enables charging of the capacitor by way of the first node; a discharge transistor connected between the first terminal of the capacitor and a second node; a discharge switch coupled between the second node and a reference voltage, wherein the discharge switch enables discharging of the capacitor by way of the second node; and a ground bias path coupled between the second node and ground, wherein the ground bias path provides a discharging bias current to the second node. A method of implementing a charge/discharge switch in an integrated circuit is also described.

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Saggart, Ireland

Ionut C Cical