Nvidia Corporation

Intel Corporation

Iole Moccagatta

Ignatius B Tjandrasuwita

Harikrishna Madadi Reddy

Zhipin Deng

Lidong Xu

Yi-Jen Chiu

Wenhao Zhang

Atul Garg

Shankar Moni

Dipankar Talukdar

Sandeep Shyamsukha

Fangwen Fu

Hiu-Fai R Chan

Tao Li

Victoria Chiu

Yumin Pan

Rajini Dasyam

This disclosure describes systems, methods, and devices related to enhanced validation of video codecs. A device may receive validation results for a video codec using a first computer programming language, the validation results indicative of invocations of functions and conditions of the code; identify, from the validation results, a first validation test that invoked a first function or condition of the code; identify, from the validation results, a second validation test that invoked the first function or condition of the code; determine, from the validation results, that the first validation test and the second validation test overlap in invoking the first function or condition of the code using the first computer programming language; and generate, based on the overlap, a first subset of the validation tests with which to validate code of the video codec using a second computer programming language.

Generation of validation test subsets to promote efficient validation of video codecs

Techniques related to motion estimation with neighbor block pattern for video coding.

Method and system of motion estimation with neighbor block pattern for video coding

Techniques related to video coding with context decoding and reconstruction bypass.

Method and system of video coding with context decoding and reconstruction bypass

A method, system, and articles of high throughput arithmetic entropy coding for video coding uses a non-framewidth raster order or non-raster order to form spatial neighbor probability contexts for entropy coding.

Method and system of high throughput arithmetic entropy coding for video coding

A method for rotating macro-blocks of a frame of a video stream. A degree of rotation for the video stream is accessed. A macro-block of the video stream is accessed. The macro-block is rotated according to the degree of rotation. The macro-block is repositioned to a new position within the frame, wherein the new position is based on the degree of rotation.

Method for rotating macro-blocks of a frame of a video stream

A video decoder architecture for processing out-of-order macro-blocks of a video stream. A microcode engine receives compressed data representing macro-blocks of a frame of a video stream, wherein at least one macro-block is received out-of-order. The microcode engine is for buffering the compressed data and for ordering the macro-blocks of the frame in raster scan order. A digital video decoder receives the macro-blocks in raster scan order and is for decoding the macro-blocks.

Video decoder architecture for processing out-of-order macro-blocks of a video stream

A hardware multi-stream multi-standard video decoder device. A command parser accesses a plurality of video streams, identifies a video encoding standard used for encoding video streams of the plurality of video streams, and interleaves portions of the plurality of video streams. A plurality of hardware decoding blocks perform operations associated with decoding the plurality of video streams, wherein different subsets of the plurality of hardware decoding blocks are for decoding video streams encoded using different video encoding standards, such that interleaved video streams are decoded by activating subsets of the plurality of hardware decoding blocks for use in decoding the plurality of video streams. A plurality of register sets store parameters associated with the plurality of video streams.

Hardware multi-stream multi-standard video decoder device

A hardware multi-standard video decoder device. A command parser accesses a video stream and identifies a video encoding standard used for encoding the video stream. A plurality of hardware decoding blocks perform operations associated with decoding the video stream, wherein different subsets of the plurality of hardware decoding blocks are for decoding video streams encoded using different video encoding standards.

Hardware multi-standard video decoder device

The present invention includes a method and system for encoding video data by accessing a picture to be encoded, wherein the picture comprises a plurality of macro-blocks. A plurality of programmable counters are associated with each macro-block to be encoded. A counter associated with a macro-block of the plurality of macro-blocks is accessed and a value of the counter is determined. The method further includes determining whether to encode the macro-block as an Intra or non-Intra based on the value of the counter. If the macro-block is encoded as Intra, its counter is reset. If the macro-block is encoded as non-Intra, its counter value is updated. The counter value may be reset with a random number. Counters can be programmed such that a region of interest is defined for updating associated macro-blocks with greater frequency.

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San Jose, CA, United States of America

Iole Moccagatta