Drexel University

Ioannis Savidis

Kyle Juretus

Divya Pathak

Vaibhav Venugopal Rao

Kapil R Dandekar

Cem Sahin

Nagarajan Kandasamy

James J Chacko

Marko Jacovic

Houman Homayoun

Md Shazzad Hossain

A state machine system on a chip presents hidden state transitions to create IC knowledge not available in a logical netlist and temporal key dependencies to increase the difficulty of executing the SAT attack. The change in the state space of a circuit over time may be used to increase circuit security. Hidden transitions that are frequency dependent, state dependent keys, and temporally dependent transition keys may be used as ways to increase security against SAT based attacks.

Enhanced circuity security through hidden state transitions

An on-chip voltage delivery method for a system includes multiple processor cores operating at multiple voltage levels. Distributed on-chip DC-DC converters as voltage regulators may deliver point of load current to the different units of a processor core operating at the same voltage level. Distributed timing sensors calibrated to generate digitized clock edge location. A power management unit may take input from the timing sensors, processes it through a particle swarm optimizer and generates digitized voltage identification code as reference to the distributed voltage regulators. The particle swarm optimizer may provide disparate voltage levels feasible for a given frequency of operation of the processor core with a provision to operate at multiple frequencies. The run-time assignment of the voltage through the particle swarm optimizer may negate the effects of transistor aging, process, temperature, and power supply noise induced variation in the load circuits, voltage regulators and sensors.

On-chip voltage assignment through particle swarm optimization

A proposed technique allows for the security of the logic cone through logic locking and secures the outputs of the circuit from the scan chain without modifications to the structure of the scan chain. Since the oracle responses in test mode do not correspond to the functional key, satisfiability (SAT) attacks are not able to leverage the responses from the scan chain. In addition, a charge accumulation circuit is developed to prevent and detect any attempt to enter the partitioned test mode while the correct circuit responses are still stored within the registers.

Reducing logic locking key leakage through the scan chain

A method for the delivery of power to subthreshold (sub-Vt) circuits uses unused current during idle-mode operation of super-threshold (super-Vt) circuits is used to supply sub-Vt circuits. Algorithmic and circuit techniques use dynamic management of idle cores when reusing the leakage current of the idle cores. A scheduling algorithm, longest idle time-leakage reuse (LIT-LR) enables energy efficient reuse of leakage current, which generates a supply voltage of 340 mV with less than &#xb1;3% variation across the tt, ff, and ss process corners. The LIT-LR algorithm reduces the energy consumption of the switch and the peak power consumption by, respectively, 25% and 7.4% as compared to random assignment of idle cores for leakage reuse. Second, a usage ranking based algorithm, longest idle time-simultaneous leakage reuse and power gating (LIT-LRPG) enables simultaneous implementation of power gating (PG) and leakage reuse in a multiprocessor system-on-chip (MPSoC) platform.

Charge recycling from idle circuits for improved energy efficiency of multi-voltage systems

A key-based interleaver for enhancement the security of wireless communication includes a physical layer communication channel key to provide security even when the software encryption key is compromised. A method of creating a secure communication link using a physical layer interleaving system includes implementing a key policy implementation that utilizes temporal dependency and interleaving bits using a flexible inter and intra-block data interleaver.

Physical layer key based interleaving for secure wireless communication

The increasing power density and, therefore, current consumption of high performance integrated circuits (ICs) results in increased challenges in the design of a reliable and efficient on-chip power delivery network. In particular, meeting the stringent on-chip impedance of the IC requires circuit and system techniques to mitigate high frequency noise that results due to resonance between the package inductance and the onchip capacitance. In this paper, a novel circuit technique is proposed to suppress high frequency noise through the use of a hyperabrupt junction tuning varactor diode as a decoupling capacitor for noise critical functional blocks. With the proposed circuit technique, the voltage droops and overshoots on the onchip power distribution network are suppressed by up to 60% as compared to MIM or deep trench decoupling capacitors of the same capacitance. In addition, there is no added latency to react to power supply noise and there is no degradation to circuit performance as compared to existing techniques in commercial products and literature.

On-chip power supply noise suppression through hyperabrupt junction varactors

A real-time workload scheduling heuristic assigns tasks to the cores such that the total load current consumption of the cores is always less than the total current capability of the under-provisioned on-chip voltage regulators. In addition, the energy-efficient scheduling of the tasks on to the cores ensures that the reconfiguration of the power delivery network is minimized. The heuristic includes DVFS management based on the unique constraints of the under provisioned voltage regulators.

Work load scheduling for multi core systems with under-provisioned power delivery

There are several approaches to encrypting circuits: combination logic encryption, encrypted gate topologies, transmission gate topologies, and key expansion of gate topologies. One of the approaches provides a circuit having a gate topology comprising a logic gate with integrated key transistors, where the key transistors comprise at least a PMOS stack and an NMOS stack. The PMOS stack comprises a first PMOS switch and a second PMOS switch, where the first and the second PMOS switches have sources to a voltage source and drains that serve as a source to a third PMOS switch. The NMOS stack comprises a first NMOS switch and a second NMOS switch, where the first and the second NMOS switches have sources to ground and drains that serve as a source to a third NMOS switch. Each of the above approaches may encrypt a circuit with certain advantages in delay and power consumption.

Reduced overhead gate level logic encryption

The transition to a horizontal integrated circuit (IC) design flow has raised concerns regarding the security and protection of IC intellectual property (IP). Obfuscation of an IC has been explored as a potential methodology to protect IP in both the digital and analog domains in isolation. However, novel methods are required for analog mixed-signal circuits that both enhance the current disjoint implementations of analog and digital security measures and prevent an independent adversarial attack of each domain. A methodology generates functional and behavioral dependencies between the analog and digital domains that results in an increase in the adversarial key search space. The dependencies between the analog and digital keys result in a 3&#xd7; increase in the number of iterations required to complete the SAT attack.

Securing analog mixed-signal integrated circuits through shared dependencies

A physical layer based technique secures wireless communication between a transmitter and receiver. The technique involves obfuscating the preamble data of the baseband signal through unique keys that are generated at the transmitter and the receiver based on channel characteristics known only to them.

Physical gate based preamble obfuscation for securing wireless communication

An approach is described for enhancing the security of analog circuits using Satisfiability Modulo Theory (SMT) based design space exploration. The technique takes as inputs generic circuit equations and performance constraints and, by exhaustively exploring the design space, outputs transistor sizes that satisfy the given constraints. The analog satisfiability (aSAT) methodology is applied to parameter biasing obfuscation, where the width of a transistor is obfuscated to mask circuit properties, while also limiting the number of keys that produce the target performance requirements.

Transistor sizing for parameter obfuscation of analog circuits

A key based technique that targets obfuscation of critical circuit parameters of an analog circuit block by masking physical characteristics of a transistor (width and length) and the circuit parameters reliant upon these physical characteristics (i.e. circuit biasing conditions, phase noise profile, bandwidth, gain, noise figure, operating frequency, etc.). The proposed key based obfuscation technique targets the physical dimensions of the transistors used to set the optimal biasing conditions. The widths and/or lengths of a transistor are obfuscated and, based on an applied key sequence, provides a range of potential biasing points. Only when the correct key sequence is applied and certain transistor(s) are active, are the correct biasing conditions at the target node set.

Protecting analog circuits with parameter biasing obfuscation

A circuit that detects the power supply voltage requirement of each voltage domain in an IC includes 1) a ring oscillator in each voltage domain, and 2) a power module. Two different circuit implementations of the power module may provide a precise reference voltage to on-chip voltage regulators (LDO or DC-DC switching buck converter). The power module supports DVFS and can provide the desired power supply voltage for advanced CMOS technology nodes (45 nm and beyond) in less than 100 ns. The voltage detection circuit clamps the voltage to the desired level to address power supply voltage variations due to PVT and ageing. The proposed technique has minimal power and area overhead to compensate for the power supply voltage variation, thus reducing power supply voltage margins which yields higher power saving.

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Wallingford, PA, United States of America

Ioannis Savidis