Broadcom Corporation

Ioannis Loukas Syllaios

Henrik Tholstrup Jensen

Stephen Wu

Georgios Sfikas

Emmanouil Frantzeskakis

Padmanava Sen

Digital phase-locked loop (PLL) with dynamic hybrid (mixed analog/digital signal) delta-sigma (&#x394;&#x3a3;) phase/frequency detector (&#x394;&#x3a3; PFD). A hybrid 2nd-order &#x394;&#x3a3; PFD may be implemented based on a continuous-time 1st-order &#x394;&#x3a3; analog-to-digital converter (ADC) enhanced to 2nd-order via closed loop frequency detection. Fine resolution encoding of the &#x394;&#x3a3; PFD output facilitates true multi-bit phase/frequency error digitization with drastically reduced &#x394;&#x3a3; quantization noise. The implementation of low complexity &#x394;&#x3a3; PFD is assisted via digital requantization and adaptive noise cancellation. The PLL includes independent frequency-locking and phase-locking operational modes and all-digital control of a digitally controlled oscillator (DCO).

Digital PLL with hybrid phase/frequency detector and digital noise cancellation

The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancellation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancellation technique to reduce phase noise introduced by the MMD.

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Costa Mesa, CA, United States of America

Ioannis Loukas Syllaios