Samsung Electronics Co., Ltd.

Samsung Sdi Co., Inc.

Insub Shin

Wook Hwan Kim

Gyuseok Han

Euisoo Jeong

Jun Seomun

Jungyun Choi

Chaehyuk Ko

Baek Soung Park

Kyungtae Do

A core-shell dye, a near-infrared absorbing resin composition including the same, a near-infrared absorbing film, an optical filter, and a CMOS image sensor, the core-shell dye includes a core represented by Chemical Formula 1; and a shell surrounding the core, the shell being represented by Chemical Formula 2;

Core-shell dye, near-infrared absorbing composition including the same, and near-infrared absorbing film

A power gating circuit includes a first switch circuit, a gate circuit, and a second switch circuit. The first switch circuit is configured to disconnect a first voltage line from a second voltage line while a logic block connected to the first voltage line is in a first operation state. The gate circuit is configured to output a control signal having a first logical value if a level of a first voltage on the first voltage line is lower than a reference level while the logic block is in the first operation state. The second switch circuit configured to connect the first voltage line to the second voltage line based on the first logical value of the control signal. The reference level is based on a type of a logic gate included in the gate circuit.

Power gating circuit for holding data in logic block

Voltage monitors include a predelay cell having an input responsive to a first clock signal. This cell is configured to generate a predelayed clock signal at an output thereof. A serially-connected string of data delay cells is provided, which has an input responsive to the predelayed clock signal. A serially-connected string of clock delay cells is provided, which has an input responsive to a second clock signal that is synchronized to the first clock signal. A plurality latches are provided. The latches have respective data inputs, which are responsive to first periodic signals generated at respective outputs of the serially-connected string of data delay cells, and respective clock/sync terminals, which are responsive to second periodic signals generated at respective outputs of the serially-connected string of clock delay cells. The latches enable loading of a delay code value, which indicates power supply voltage variation.

Voltage monitor for generating delay codes

Growing community of inventors

Suwon-si, South Korea

Insub Shin