Samsung Electronics Co., Ltd.

Insu Choi

Wonjae Shin

Dae-Jeong Kim

Sung-Joon Kim

Deokho Seo

Yongjun Yu

Changmin Lee

Minsu Kim

Dohan Kim

Namhyung Kim

Do-Han Kim

Daejeong Kim

Chanik Park

Tae-Kyeong Ko

Nam Hyung Kim

Youngjin Cho

Ho-Young Reho Lee

Ho-young Lee

Ki-Seok Oh

Sun-Young Lim

Ilho Kim

Sungyong Seo

Kyung-Hee Han

Jinwoo Kim

Minsoo Kim

Donghoon Lee

Hoyoung Lee

Kwanghee Lee

Dongyoon Kim

Hyun-Sung Shin

Chaeeun Lee

Heedong Kim

Do-han Kim

Ilguy Jung

Changho Yun

Jongyoung Lee

Wooseop Kim

Kyungjin Park

Jiseok Kang

Jinhun Jeong

Yunmi Hwang

Jihyuk Oh

Mijin Lee

Minhyouk Kim

Yeonhwa Lee

Kideok Han

Seung Ju Lee

Hui-Chung Byun

Chinam Kim

Sung-joon Kim

Jongwon Jeong

Jaein Song

Hyan Suk Lee

Minsu Bae

Ilwoong Seo

Taekyeong Ko

Kyeongjin Cho

Bobae Kim

Byeongnoh Kim

Yukyoung Kim

Byungjik Kim

Youjin Jang

Seungman Shin

A memory system including a memory device that receives a plurality of signals including a post package repair (PPR) command from a host, wherein the memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a plurality of redundancy memory cells connected to one or more redundancy word lines and the plurality of bit lines, and anti-fuse memory cells, and a PPR control circuit that transmits to the host whether a PPR operation on a defective memory cell of the memory cell array has passed.

Memory system, operating method of the same, and controller of memory device

A memory device includes; a memory cell array, and a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table. The command/address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.

Memory device including address table and operating method for memory controller

A method for preparing error recovery of a memory device included in a memory system includes performing a training operation of the memory device upon power-on of the memory system, booting an operating system into a normal mode by operating the memory device using a selected operation frequency of a plurality of operation frequencies based on results of the training operation, detecting an error frequency among the plurality of operation frequencies in response to a change of the selected operation frequency of the memory device by the operating system, the error frequency being an operation frequency which causes at least one error in the memory device, and storing information regarding the detected error frequency in a first register included in a memory controller associated with the memory device.

Memory system including memory controller and memory device and method for recovering from an error thereof

An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.

Operation method of memory module, operation method of memory controller, and operation method of memory system

Disclosed is an electronic device including a memory module that includes at least one dynamic random access memory, and a processor configured to access the memory module, determine a corrected error count associated with an address of a corrected error in response to the corrected error being detected when data are read from the memory module, read an error log associated with the corrected error, determine a risk level of the corrected error based on the error log, and schedule a post package repair (PPR) for the address of the corrected error in response to the risk level of the corrected error being high.

Electronic device managing corrected error and operating method of electronic device

A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.

Memory device, memory module including the memory device, and operating method of memory controller

A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.

Memory module, memory system, and operation method of memory controller

An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

Electronic device, operation method of host, operation method of memory module, and operation method of memory device

A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.

Memory device capable of outputting fail data in parallel bit test and memory system including the memory device

Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

Accelerator controlling memory device, computing system including accelerator, and operating method of accelerator

Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

Memory device skipping refresh operation and operation method thereof

A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.

Method for accessing semiconductor memory module

A memory module including at least one memory and a memory control circuit to control the at least one memory and to generate an internal operation request including an information regarding internal operation time when the memory module need the internal operation time. The memory control circuit is to transfer the internal operation request to an external device, to receive a first command from the external device in response to the internal operation request and including an information of whether the internal operation time is approved, and to perform the internal operation during the internal operation time based on the first command.

Memory module and memory system relating thereto

Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

Memory systems having semiconductor memory modules therein that support page fault processing

A method of operating a system running a virtual machine that executes an application and an operating system (OS) includes performing first address translation from first virtual addresses to first physical addresses, identifying faulty physical addresses among the first physical addresses, each faulty physical address corresponding to a corresponding first physical address associated with a faulty memory cell, analyzing a row address and a column address of each faulty physical address and specifying a fault type of the faulty physical addresses based on the analyzing of the row address and the column address of each faulty physical address, and performing second address translation from second virtual addresses to second physical addresses based on a faulty address, thereby excluding the faulty address from the second physical addresses.

Handling operation system (OS) in system for predicting and managing faulty memories based on page faults

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Hwaseong-si, South Korea

Insu Choi