Samsung Electronics Co., Ltd.

Inseak Hwang

Inho Kim

Jonghyuk Park

Byoungho Kwon

Yanghee Lee

Yunjung Choi

Hyesung Park

Jin-Woo Bae

Mongsup Lee

Kivin Im

Dongbok Lee

Yoonho Son

Wonjun Lee

Kyunghyun Kim

Yongsun Ko

Sukhun Choi

Sang-jun Lee

Sang-Jun Lee

Jinhye Bae

Shinhee Han

Byoung-Yong Gwak

Hyunchul Shin

Yoonsung Han

Chan Min Lee

Woogwan Shim

Changkyu Lee

Kwangwook Lee

Munkwon Kang

Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.

Semiconductor devices having nonlinear bitline structures

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a semiconductor substrate including a first region and a second region, a dummy separation pattern provided on the second region of the semiconductor substrate to have a recessed region at its upper portion, a first electrode provided on the first region of the semiconductor substrate, a dielectric layer covering the first electrode, a second electrode provided on the dielectric layer, and a remaining electrode pattern provided in the recessed region. The second electrode and the remaining electrode pattern may be formed of a same material.

Semiconductor device and method of fabricating the same

A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion.

Method of fabricating semiconductor device

Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two-adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.

Manufacturing a MRAM device may include removing etch residues from a magnetic tunnel junction (MTJ) pattern in the presence of an atmosphere. The removing may include applying a cleaning solution to one or more surfaces of the MTJ pattern. Manufacturing the MRAM device may include removing an oxide layer based on sputter etching of the MTJ pattern. The etch residues may be removed such that the oxide layer is formed. Removing the etch residues may include applying a cleaning solution to the MTJ pattern. The etch residues may be removed in the presence of an atmosphere. The MTJ pattern may be formed based on patterning an MTJ layer in a vacuum state such that the etch residues are formed on a surface of the MTJ pattern.

Magneto-resistance random access memory device and method of manufacturing the same

A substrate having an insulating layer including an oxide is loaded into a chamber, and at least a part of the insulating layer is removed by injecting a process gas including an etching source gas into the chamber. The removal process is performed in a pulse type in which a first period and a second period are repeated a plurality of times. The etching source gas is supplied at a first flow rate during the first period and is supplied at a second flow rate less than the first flow rate during the second period. A temperature of the inside of the chamber remains at 100&#xb0; C. or more during the removal process.

Method of manufacturing semiconductor devices

A semiconductor device may include a substrate including an active pattern delimited by a device isolation pattern, a gate electrode crossing the active pattern, a first impurity region and a second impurity region in the active pattern on both sides of the gate electrode, a bit line crossing the gate electrode, a first contact electrically connecting the first impurity region with the bit line, and a first nitride pattern on a lower side surface of the first contact. A width of the first contact measured perpendicular to an extending direction of the bit line may be substantially equal to that of the bit line.

Provided is a method of fabricating a semiconductor device. The method includes: preparing a substrate with an etching target, and etching the etching target through a plasma-free etching process that uses an etching gas including one of interhalogen compound, F, XeFand combinations thereof.

Methods of fabricating semiconductor devices

A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer.

The present disclosure describes methods of fabricating a semiconductor device. An exemplary method includes forming a metal pattern on a substrate and etching the metal pattern using an etchant including at least an alkaline solution and an oxidant to form a metal electrode, where at least a portion of the surface of the metal electrode is uneven.

Growing community of inventors

Suwon-si, South Korea

Inseak Hwang