Semiconductor Components Industries, LLC

Infineon Technologies Ag

Inpil Yoo

JooYang Eom

Jerome Teysseyre

Seungwon Im

Andreas Grassmann

Maria Cristina Estacio

Oseob Jeon

Michael John Seddon

Tomas Manuel Reiter

Keunhyuk Lee

Wolfram Hable

Christian Neugirg

Ottmar Geitner

Carlos Castro Serrato

Frank Winter

Dongwook Kang

Alexander Schwarz

Tom Roewe

Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

Semiconductor packages using package in package systems and related methods

According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.

Power module package for direct cooling multiple power modules

Implementations of a semiconductor package may include one or more power semiconductor die included in a die module; a first heat sink directly coupled to one or more source pads of the die module; a second heat sink directly coupled to one or more drain pads of the die module; a gate contact coupled with one or more gate pads of the die module; and a coating coupled directly to the die module. The gate contact may be configured to extend through an immersion cooling enclosure.

Dual side direct cooling semiconductor package

A method includes disposing a first direct bonded metal (DBM) substrate substantially parallel to a second DBM substrate a distance apart to enclose a space. The method further includes disposing at least a semiconductor die in the space, and bonding the semiconductor die to the first DBM substrate using a first adhesive layer without an intervening spacer block between the semiconductor die and the first DBM substrate, and bonding the semiconductor die to the second DBM substrate using a second adhesive without an intervening spacer block between the semiconductor die and the second DBM substrate.

High power module package structures

Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.

Submodule semiconductor package

Implementations of a clip may include a first copper layer directly bonded to a first side of a ceramic layer, a second copper layer directly bonded to a second side of the ceramic layer, the second side of the ceramic layer opposite the first side of the ceramic layer, and a plurality of channels partially etched into a thickness of the second copper layer.

Clips for semiconductor package and related methods

In one general aspect, an apparatus can include a substrate, a semiconductor die coupled with a first surface of the substrate, and a metal layer disposed on a second surface of the substrate. The second surface can be opposite the first surface. The apparatus can also include a plurality of metal fins coupled with the metal layer, and a metal ring coupled with the metal layer. The metal ring can surround the plurality of metal fins.

Heat transfer for power modules

In accordance with an embodiment, a method includes: monitoring a temperature difference between two double-side cooled (DSC) power modules of a plurality of DSC power modules arranged in stacks of DSC power modules; comparing the temperature difference with a first temperature threshold; detecting a cooling pipe system blockage when the temperature difference is above the first temperature threshold; and after detecting the cooling pipe system blockage, disabling gate driver circuits coupled to the plurality of DSC power modules or operating the DSC power modules in a low-power mode. Each stack includes a plurality of DSC power modules. Each DSC power module has a top surface and a bottom surface, which are each thermally coupled with one or more cooling channels of a cooling pipe system. The two DSC power modules are thermally coupled with a same cooling channel of the one or more cooling channels.

Temperature sensing and fault detection for paralleled double-side cooled power modules

A cooling apparatus includes a discrete module and a plastic housing. The discrete module includes a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and protruding out of the mold compound and a first cooling plate at least partly uncovered by the mold compound. The plastic housing surrounds the periphery of the discrete module. The plastic housing includes a first singular plastic part which receives the discrete module and a second singular plastic part attached to a periphery of the first plastic part. The second plastic part has a cutout which exposes at least part of the first cooling plate and a sealing structure containing a sealing material which forms a water-tight seal around the periphery of the discrete module at a side of the discrete module with the first cooling plate.

Semiconductor module cooling system

A cooling apparatus is manufactured by: receiving a discrete module by a first singular part, the discrete module including a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and protruding out of the mold compound, and a first cooling plate at least partly uncovered by the mold compound; attaching a second singular part to a periphery of the first part to form a housing, the housing surrounding a periphery of the discrete module, the second part having a cutout which exposes the first cooling plate and a sealing structure facing a side of the discrete module with the first cooling plate; and filling the sealing structure with a sealing material which forms a water-tight seal around the periphery of the discrete module at the side of the discrete module with the first cooling plate.

Method of manufacturing a cooler for semiconductor modules

A cooling apparatus includes a plurality of discrete modules and a plastic housing. Each module includes a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and protruding out of the mold compound and a first cooling plate at least partly uncovered by the mold compound. The plastic housing surrounds the periphery of each module to form a multi-die module. The plastic housing includes a first singular plastic part which receives the modules and a second singular plastic part attached to a periphery of the first plastic part. The second plastic part has cutouts which expose the first cooling plates and a sealing structure containing a sealing material which forms a water-tight seal around the periphery of each module at a side of the modules with the first cooling plates.

Plastic cooler for semiconductor modules

An electronic module is provided, which comprises a first carrier; an electronic chip comprising at least one electronic component and arranged on the first carrier; a spacing element comprising a surface arranged on the electronic chip and being in thermal conductive connection with the at least one electronic component; a second carrier arranged on the spacing element; and a mold compound enclosing the electronic chip and the spacing element at least partially; wherein the spacing element comprises a material having a CTE value being matched with at least one other CTE.

Growing community of inventors

Unterhaching, Germany

Inpil Yoo