Samsung Electronics Co., Ltd.

Inmo Kim

Sujeong Kim

Daeseok Byeon

Taemin Ok

A memory device includes: a memory cell region including gate electrodes spaced apart from each other on a first semiconductor substrate to be stacked, and channel structures; and a peripheral circuit region including upper metal lines disposed above a second semiconductor substrate, disposed below the memory cell region. The first semiconductor substrate includes first regions, having a first value corresponding to a distance between the first semiconductor substrate and the upper metal lines, and second regions having a second value, lower than the first value. A reference voltage for operating the memory device is transmitted to at least one of the first upper metal lines, disposed below the first region. Accordingly, coupling capacitance for a significant signal may be reduced while maintaining a length of a connection portion and the magnitude of resistance of a common source line. Furthermore, an error rate of the memory device may be reduced.

Memory device

An integrated circuit device includes a semiconductor substrate having components of a peripheral circuit structure formed in and on a surface of the semiconductor substrate. The peripheral circuit structure comprising a plurality of protective antenna diodes therein. A memory cell array structure is provided on at least a portion of the peripheral circuit structure. A charge accumulating conductive plate is provided, which extends between the peripheral circuit structure and the memory cell array structure. The conductive plate is electrically connected to current carrying terminals of the antenna diodes within the peripheral circuit structure. The conductive plate may have a generally rectangular planar shape with four corners, and the antenna diodes may be arranged into four groups, which extend between respective corners of the conductive plate and the semiconductor substrate.

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Hwaseong si, South Korea

Inmo Kim