Skhynix Inc.

InHwa Jung

SungWoo Kim

Kwandong Kim

A semiconductor integrated circuit includes a sense amplifier circuit suitable for generating differential output signals by sensing and amplifying a level difference of differential input signals in response to a clock signal, and outputting the differential output signals to first and second nodes, respectively, a latch circuit suitable for feeding back and latching the differential output signals between the first and second nodes, and a control circuit suitable for controlling the feedback of the differential output signals between the first and second nodes in response to an initialization signal.

Sense amplifier based flip-flop capable of resolving metastable state by removing unintentional current from output nodes

A level shifter includes: a first inverter suitable for inverting a signal of a first node based on a first pull-up voltage and a first pull-down voltage; a second inverter suitable for inverting the signal of the first node based on a second pull-up voltage and a second pull-down voltage; and a capacitor coupled between an output node of the first inverter and an output node of the second inverter.

Level shifter

An integrated circuit which adjusts a period for enabling a transmitter, and includes a data delay circuit delaying data to generate transmission data; a transmission/reception terminal; a receiver receiving reception data transferred to the transmission/reception terminal, in response to a reception enable signal; a transmitter transmitting the transmission data to the transmission/reception terminal in response to a transmission enable signal; a shift circuit generating a plurality of preliminary transmission enable signals by sequentially delaying a signal; a phase comparison circuit comparing a phase of each of the plurality of preliminary transmission enable signals and a phase of the transmission data; and a selection circuit selecting one of the plurality of preliminary transmission enable signals as a transmission enable signal according to a phase comparison result of the phase comparison circuit. Since only one phase comparison circuit is used, a circuit area for generating the transmission enable signal may be reduced.

Transmission enable signal generation circuit and integrated circuit

A delay circuit may include a delay path including a fine delay line and a coarse delay line, a replica delay path including a replica fine delay line and a replica coarse delay line, and a tuning unit that compares a phase of a first signal obtained by delaying an input signal through the delay path with a phase of a second signal obtained by delaying the input signal through the replica delay path, and generates a tuning code in a tuning mode.

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Gyeonggi-do, South Korea

InHwa Jung