Samsung Electronics Co., Ltd.

Inho Kang

YongSung Cho

Jeunghwan Park

Jinwoo Park

Yongsung Cho

Taehyo Kim

Jinyoung Chun

Daeseok Byeon

Jaewon Lee

Ilhan Park

Jeongsu Kim

Gyosoo Choo

Jeongmi Cho

Dongha Shin

Ansoo Park

Beakhyung Cho

Min-Hwi Kim

Jeawon Jeong

Insu Kim

Jaehue Shin

Haechang Rim

A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected to the plurality of memory cells via a plurality of bit lines, and a plurality of cache latches respectively corresponding to the plurality of page buffer units. Each of the plurality of page buffer units includes a pass transistor that is connected to a corresponding sensing node and is driven according to a pass control signal, and the memory device is configured such that in a data sensing period, a sensing node of a selected page buffer unit among the plurality of page buffer units is actively connected to a sensing node of an unselected page buffer unit among the plurality of page buffer units.

Memory device including page buffer circuit

Provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.

Non-volatile memory device with high voltage region and low voltage region

A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit provided in a page buffer region including a main region and a cache region provided in a first horizontal direction, and including a first page buffer unit and a second page buffer unit adjacent to each other in a second horizontal direction in the main region. A first sensing node of the first page buffer unit includes a first lower metal pattern, and a first upper metal pattern, and electrically connected to the first lower metal pattern. A second sensing node of the second page buffer unit includes a second lower metal pattern, and a second upper metal pattern, electrically connected to the second lower metal pattern, and not adjacent to the first upper metal pattern in the second horizontal direction.

Page buffer circuit and memory device including the same

A page buffer circuit includes a plurality of page buffers connected to a plurality of bitlines. Each of the plurality of page buffers includes a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node, and a dynamic latch circuit configured to store data in a storage node. Each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node.

Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

A method and apparatus for updating a dictionary, by which documents of interest of a user are extracted through a network and a dictionary is updated with individual names and coined words extracted from the web documents, are provided. The dictionary updating method includes: extracting a document of interest of a user in each predetermined extraction period from a predetermined server connected to a dictionary updating system through a network, and extracting candidate unregistered words existing in the extracted document according to predetermined unregistered word extraction rules; based on information on appearance frequencies of the candidate unregistered words retrieved from the document, extracting unregistered words among the candidate unregistered words and extracting candidate semantic classes of the unregistered word; with usage examples of the unregistered word obtained through a searching unit, according to a predetermined unregistered word verification method, verifying the unregistered word and determining the semantic class of the verified unregistered word; and updating the dictionary updating system with the verified unregistered word and the semantic class of the verified unregistered word.

Periodically extracting and evaluating frequency of occurrence data of unregistered terms in a document for updating a dictionary

A speech processing apparatus, medium, and method recognizing speech and responding to the speech. The speech processing apparatus may includes an entity extracting unit which extracts entity information and an upper entity corresponding to the entity information from input speech, a focus determination unit which determines a focus using the extracted entity information requiring a response, a mapping unit which maps lower entity corresponding to the focus with the extracted entity information, and a recognition unit which recognizes a result of arranging the extracted entity information according to semantic association among the lower entities as the input speech. Thus, the speech processing apparatus can accurately recognize grammatically correct speech as well as grammatically incorrect speech and then respond to the speech.

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Yongin-si, South Korea

Inho Kang