Samsung Electronics Co., Ltd.

Ingyu Baek

Minyoung Park

Doowon Kwon

Hyunjun Sim

Jinshi Zhao

Jinyong Choi

Hongsik Yoon

Hyunsu Ju

Seungsik Kim

Hyunchul Kim

Yeong-taek Lee

Donghun Kwak

Sunjung Kim

Chanjin Park

Kyungtae Nam

Daehoon Kim

Cheon An Lee

Jin-Shi Zhao

Seonggeon Park

SeungSik Kim

Min Kyu Yang

Seunghan Yoo

HongSik Yoon

Eunmi Kim

Joosung Moon

Hong Sik Yoon

Jiyoun Song

Haemin Lim

KyungMin Kim

Minjung Chung

Hyun Jun Sim

Provided is an image sensor including a semiconductor substrate having first and second surfaces, transistors on the first surface, first and second lower pad electrodes apart from each other on a first interlayer insulating film covering the transistors, a mold insulating layer on the first and second lower pad electrodes, a first lower electrode inside a first opening passing through the mold insulating layer on the first lower pad electrode, a second lower electrode inside a second opening passing through the mold insulating layer on the second lower pad electrode, a dielectric film and an upper electrode on the first and second lower electrodes, a first contact plug passing through the mold insulating layer and connected to the first lower pad electrode, and a second contact plug passing through the mold insulating layer and connected to the second lower pad electrode.

Image sensor

An image sensor is provided and includes a photoelectric conversion layer, an integrated circuit layer, and a charge storage layer. The photoelectric conversion layer includes a pixel separation structure defining pixel regions, each including a photoelectric conversion region. The integrated circuit layer read charges from the photoelectric conversion regions. The charge storage layer includes a stacked capacitor for each of the pixel regions. The stacked capacitor includes a lower pad electrode, an intermediate pad electrode, an upper pad electrode, a contact plug connecting the upper pad electrode to the lower pad electrode, a first lower capacitor structure connected between the lower pad electrode and the intermediate pad electrode, and an upper capacitor structure connected between the intermediate pad electrode and the upper pad electrode. The upper capacitor structure is stacked on the lower capacitor structure to partially overlap the lower capacitor structure when viewed in plan view.

An image sensor includes a first layer including pixels in a pixel array, and a first logic circuit configured to control the pixel array. Each of the pixels include at least one photodiode configured to generate a charge in response to light, and a pixel circuit configured to generate a pixel signal corresponding to the charge. A second layer includes a second logic circuit that is connected to the pixel array and the first logic circuit and is on the first layer. A third layer includes storage elements that are electrically connected to at least one of the pixels or the first logic circuit and an insulating layer on the storage elements. A lower surface of the insulating layer is attached to an upper portion of the first layer, and an upper surface of the insulating layer is attached to a lower portion of the second layer.

Image sensor and manufacturing method of the same

An imaging device includes a pixel array with first and second pixels respectively having first and second conversion gains connected to row and column lines; a row driver determining a selection row line among the row lines; a readout circuit obtaining first and second pixel signals from first and second pixels connected to the selection row line; a column driver generating first and second image data from the first and second pixel signals; and an image signal processor using the first and second image data to generate an object image. The second pixels include an expansion capacitor connected between a floating diffusion node and a ground node. Exposure time of the first pixels is equal to or longer than exposure time of the second pixels. An area of a light receiving region of the first pixels is equal to an area of a light receiving region of the second pixels.

Image sensor and imaging device including the same

An image sensor is provided. The image sensor includes a first substrate; a plurality of photoelectric conversion units positioned in the first substrate; a first connection layer disposed on the first substrate; a plurality of first pixel pads disposed on the first connection layer; a plurality of first peripheral pads disposed on the first substrate; a plurality of second pixel pads respectively positioned on the plurality of first pixel pads; a plurality of second peripheral pads respectively positioned on the plurality of first peripheral pads; a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads; a device disposed on the second connection layer; and a second substrate disposed on the second connection layer and the device, wherein a pitch of the plurality of first pixel pads is substantially the same as a pitch of the plurality of pixel regions of the first substrate.

An image sensor includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a photoelectric conversion layer in the semiconductor substrate, transistors on the first surface of the semiconductor substrate, a first interlayer insulation layer on the transistors, a first lower pad electrode and a second lower pad electrode spaced apart from the first lower pad electrode on the first interlayer insulation layer, a mold insulation layer on the first and second lower pad electrodes, first and second lower electrodes in the mold insulation layer, a dielectric layer on the first and second lower electrodes, an upper electrode on the dielectric layer, and an upper pad electrode connected to the upper electrode and including a different conductive material from the first and second lower pad electrodes. The first lower electrodes are on the first lower pad electrode, and the second lower electrodes are on the second lower pad electrode.

Disclosed is an image sensor comprising a first substrate including a plurality of pixels, a photoelectric conversion region in the first substrate at each of the pixels, a first capacitor on the first substrate, and a shield structure spaced apart from and surrounding the first capacitor.

Image sensor including a shield structure

A method of operating a resistive non-volatile memory can be provided by applying a forming voltage across first and second electrodes of a selected memory cell in the variable resistance non-volatile memory device during an operation to the selected memory cell. The forming voltage can be a voltage level that is limited to less than a breakdown voltage of an insulation film included in selected memory cell between a variable resistance film and one of first electrode. Related devices and materials are also disclosed.

Methods of operating variable resistance memory devices

A method of operating a variable resistance memory device comprises determining a level of an access voltage based on a number of rows or columns of a cell array, and supplying the access voltage having the determined level to the cell array.

Variable resistance memory device and related method of operation

Resistive memory driving methods are provided. The methods may include applying an operating voltage set according to a mode of operation to a selected word line among the plurality of word lines and a selected bit line among the plurality of bit lines within a line delay period.

Resistive memory devices and methods of operating the same

Three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include first, second and third conductive lines disposed at different vertical levels to define two intersections, and two memory cells disposed at the two intersections, respectively. The first and second conductive lines may extend parallel to each other, and the third conductive line may extend to cross the first and second conductive lines. The first and second conductive lines can be alternatingly arranged along the length of third conductive line in vertical sectional view, and the third conductive line may be spaced vertically apart from the first and second conductive lines.

Three-dimensional semiconductor memory devices having double cross point array and methods of fabricating the same

A semiconductor memory device includes a stacked structure including a plurality of wordline structures sequentially stacked that each include: a plurality of wordlines with sidewalls and extending in a first direction on the substrate, and a connecting pad extending in a second direction on the substrate and being connected in common to the plurality of wordlines. A plurality of interconnections at a height over the substrate are connected to the connecting pads of the wordline structures, respectively. The device further includes bitlines substantially vertical to a top surface of the substrate and crossing one of the sidewalls of the plurality of wordlines, and memory elements between the bitlines and the plurality of wordlines, respectively. A length of the connecting pad in the second direction is substantially equal to a product of a minimum pitch between the interconnections and a stack number of one of the plurality of wordlines.

Semiconductor memory devices

Provided are resistance memory devices and methods of forming the same. The resistance memory devices include a first electrode and a second electrode on a substrate, a transition metal oxide layer interposed between the first electrode and the second electrode, an electrolyte layer interposed between the second electrode and the transition metal oxide layer, and conductive bridges having one end that is electrically connected to the second electrode on the electrolyte.

Resistance memory devices and methods of forming the same

A semiconductor memory device includes a first conductive line, a second conductive line crossing over the first conductive line, a resistance variation part disposed at a position in which the second conductive line intersects with the first conductive line and electrically connected to the first conductive line and the second conductive line and a mechanical switch disposed between the resistance variation part and the second conductive line. The mechanical switch includes a nanotube.

Growing community of inventors

Seoul, South Korea

Ingyu Baek