International Business Machines Corporation

Ingrid E Magdo

Steven Magdo

Shakir A Abbas

Shashi D Malaviya

George R Goth

Hans S Rupprecht

Richard C Joy

Alfred Phillips, Jr

Armin Bohg

Wei-Kan Chu

William J Nestork

Theodore William Kwap

Douglas W Ormond

A dielectrically isolated semiconductor device which is substantially planar can be manufactured. The structure is useable for integrated circuits wherein a significant savings in surface area can be obtained over prior techniques. The structure is particularly useful for bipolar integrated circuits wherein a semiconductor substrate with an epitaxial layer thereon contains a buried region partially in the substrate and in the epitaxial layer. The emitter and base regions are located in the epitaxial layer above the buried region. The dielectrically isolating region surrounds the emitter and base region at the surface and extends to a depth wherein it intersects with the buried region to fully isolate the device. The buried region is connected as the collector element of the transistor.

Dielectric isolation for high density semiconductor devices

A method for selectively depositing a plurality of metal layers on a substrate. The method includes the steps of depositing at least one layer of blanket metal on a surface of a substrate, building a lift-off stencil over the blanket metal, depositing at least one layer of redundant metal over the lift-off stencil, depositing a first etch-resistant barrier over the redundant metal, removing the lift-off stencil and the overlying layers of redundant metal and the etch-resistant barrier, depositing a second etch-resistant barrier over the blanket metal and the first etch-resistant barrier, and then reactive ion etching (RIE) the second etch-resistant barrier so as to expose the blanket metal and at least partially remove the second etch-resistant barrier from the first etch-resistant barrier. A final step of the method includes etching the blanket metal. Also disclosed is a metallurgical structure for a packaging substrate. The metallurgical structure includes layers of blanket metal and redundant metal. The redundant metal has an electrically isolating coating on its side but not on its top surface, thereby facilitating the electrical contact of the redundant metal with an electrical component.

Method for producing a plurality of layers of metallurgy

A method of forming on a substrate a pattern of structures having a thickness on the order of one micron or less. A first insulating layer is formed on a major surface of a substrate, for example, a silicon body. A polycrystalline silicon layer is formed thereover and openings are formed therein by reactive ion etching to provide substantially horizontal surfaces and substantially vertical sidewalls. The vertical sidewalls of the openings are formed at the desired locations of the narrow dimensioned structures. A second, conformal insulating layer is then formed followed by a reactive ion etching step which substantially removes the horizontal portions of the second insulating layer. The remaining polycrystalline silicon layer is removed to leave a pattern of self-supporting narrow dimensioned dielectric regions on the major surface of the substrate. The narrow dimensioned dielectric regions can be used as a mask to form narrow structures in the substrate. Alternatively, a self-aligned pattern of metallization can be formed using the narrow dimensioned dielectric regions to provide sub-micron metal-to-metal spacing.

Self-aligned metal process for integrated circuit metallization

A self-aligned metal integrated circuit structure is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The remaining polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between. The surface is planarized, leaving the structure of metal filling the regions between the pattern of dielectric material.

Self-aligned metal structure for integrated circuits

A PNP semiconductor device and a manufacturing method therefore. In the method, a window is formed on the surface of a semiconductor substrate having an N-type base region formed therein. A polycrystalline layer is formed on the base region in the window. The polycrystalline silicon layer is ion implanted under specific predetermined conditions with a P-type doping ion. The P-type doping ion is diffused by an annealing treatment under predetermined conditions into the base region to form a shallow emitter region.

Method for manufacturing vertical PNP transistor with shallow emitter

A self-aligned metal field effect transistor is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar.

Self-aligned metal field effect transistor integrated circuit

Disclosed is a method of making on a common substrate complementary vertical NPN and PNP transistors having matched high performance characteristics. A barrier region of a first conductivity type is formed on a semiconductor substrate of a second conductivity type. Then, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate. In a preferred embodiment the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base. The polycrystalline silicon is doped with a P-type dopant. Thereafter the transistor structure is subjected to conditions whereby the doping ions contained in the polycrystalline silicon layer are driven into the epitaxial layer to provide a shallow emitter region without effecting dislocations in the silicon lattice of the epitaxial layer.

Complementary transistor structure and method for manufacture

A transistor structure is provided with an emitter which is formed from non-monocrystalline silicon which is caused to be converted to monocrystalline silicon during the manufacture of the transistor. In the process of manufacturing the present semiconductor structure, a subcollector is formed in a semiconductor substrate. The subcollector dopant out diffuses into a subsequently deposited epitaxial layer. A base region is formed in the epitaxial layer of a conductivity type opposite that of the conductivity type of the subcollector. This results in a PN junction between the base region and the out diffused subcollector impurities forming the collector of the transistor. A layer of non-monocrystalline silicon is deposited on the epitaxial layer. At least a portion of the non-monocrystalline silicon forms a precursor for an emitter region which is contiguous to but vertically displaced from the surface of the base region. The emitter precursor is then bombarded with ions of a conductivity type that is the same as the conductivity type of the subcollector. The ion bombardment is at a dose and energy level sufficient to displace a portion of the Gaussian distribution of the ions across the interface between the non-monocrystalline layer and the epitaxial layer and into the base region. Thereafter, the structure is annealed by suitable means to drive a portion of the ions deeper into the base region and to convert the non-monocrystalline silicon of the emitter precursor into a monocrystalline emitter region.

Method of making emitter regions by implantation through a

A self-aligned metal process is described which achieves self-aligned metal silicon contacts and micron-to-submicron contact-to-contact and metal-to-metal spacing by use of the pattern of dielectric material having a thickness in the order of a micron or less. The pattern of recessed oxide isolation to device area is also self-aligned by this process. The process results in substantially planar integrated circuit structure. The process is applicable to either a bipolar integrated circuit either bipolar or MOS field effect transistor integrated circuits.

Method to fabricate stud structure for self-aligned metallization

A self-aligned metal process is decribed which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The remaining polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between. The surface is planarized leaving the structure of metal filling the regions between the pattern of dielectric material.

A dielectrically isolated semiconductor device can be manufactured. The structure is useable for integrated circuits, including field effect and/or bipolar transistors, wherein a significant savings in surface area and reduction in capacitances can be obtained over prior techniques. The method involves forming a layer of dielectric material upon a semiconductor body, having a diffused region where a bipolar device is to be formed, and then forming an opening in the layer to expose a part of the surface of the diffused region of the semiconductor body. An epitaxial layer of silicon is deposited on top. Single crystal silicon will grow over the exposed silicon area and if a diffused region is present in the substrate a pedestal will outdiffuse through the same area from the buried diffused region. Polycrystalline silicon will grow on top of the dielectric material. The pedestal is formed in a single crystal epitaxial layer of another impurity type. Two other active elements of a bipolar transistor, such as the emitter and intrinsic base regions, are then formed in the same single crystal epitaxial layer while the inactive area, such as the extrinsic base, is formed in polycrystalline silicon. A reach through is made through the dielectric layer to the third element of the transistor, that is collector region.

Dielectrically isolated semiconductor devices

A process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistors. The insulation between the contacts and the metal is dielectric material having a thickness dimension about a micron or less. The structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the layer by reactive ion etching which results in the structure having horizontal surfaces and vertical surfaces. The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the horizontal surfaces and vertical surfaces. Reactive ion etching of this second insulating layer moves the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation. The remaining polycrystalline layer is removed to leave the narrow regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions and form the gate electrodes.

Self-aligned metal process for field effect transistor integrated

Complementary, vertical bipolar NPN and PNP transistors are fabricated on the same monolithic semiconductor substrate which have matched high performance characteristics. A method for fabricating such complementary devices is also provided. In the method, a barrier region of a first conductivity type is formed on the surface of the monocrystalline semiconductor substrate doped with a second conductivity type. After an annealing heat treatment to drive in the doping ions of the barrier region, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. The collector region for the other complementary transistor is formed within at least one other isolation region. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate. To provide improved PNP transistor performance, the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base. The polycrystalline silicon is doped with a P-type dopant. Thereafter the transistor structure is subjected to conditions whereby the doping ions contained in the polycrystalline silicon layer are driven into the epitaxial layer to provide a shallow emitter region without effecting dislocations in the silicon lattice of the epitaxial layer.

Complementary transistor structure

A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing in the Integrated Injection Logic (I.sup.2 L) technology. The method involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. The first insulating layer is removed in areas designated to contain integrated injection logic devices. A layer of highly doped polycrystalline silicon is formed thereover. The conductivity of the polycrystalline silicon is opposite to that of the silicon body. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are formed in areas designated to be the base of the lateral injector transistor of the integrated circuit. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The method continues using similar procedures to form the remaining elements of the I.sup.2 L device structure.

Self-aligned metal process for integrated injection logic integrated

Structure: An integrated circuit structure with full dielectric isolation comprising a supporting substrate having a planar surface of dielectric material and a semiconductor layer on said dielectric surface which forms a planar interface with the surface. Regions of oxidized silicon extend through the layer from said interface, surrounding and dielectrically isolating pockets of silicon in the layer; the oxidized silicon regions extend to the upper surface of the semiconductor layer where they are substantially co-planar with the silicon pockets. The devices of the integrated circuit are formed in said silicon pockets. Method: The structure is fabricated by a novel method wherein a lightly doped silicon layer is deposited on a highly doped silicon substrate; surrounding oxidized silicon regions are then formed by selectively thermally oxidizing portions of the silicon layer to form oxide regions which are co-extensive with the oxidized areas and, thus, are co-planar with the remaining silicon pockets at both surfaces of the layer; a member having a dielectric surface interfacing with the silicon layer is formed, and the silicon substrate is removed by preferential electrochemical anodic etching to leave the silicon layer having the oxidized regions surrounding spaced silicon pockets mounted on said member.

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Hopewell Junction, NY, United States of America

Ingrid E Magdo