Globalfoundries Inc.

Ingolf Lorenz

Ulrich G Hensel

Michael Zier

Jongwook Kye

Mahbub Rashed

Suresh Venkatesan

Scott C Johnson

Subramani Kengeri

Jason Eugene Stephens

Marc Laurent Tarabbia

Navneet Jain

Stefan G Block

Yunfei Deng

Jürgen Faul

David Doman

Yuansheng Ma

Irene Y Lin

Chinh Nguyen

Jeff Kim

Christian Haufe

Rod Augur

Seung-Hyun Rhee

James B Gullette

Larry Ho

Haritez Narisetty

An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.

Contacting SOI subsrates

It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.

Reducing antenna effects in SOI devices

A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

Semiconductor device having contact layer providing electrical connections

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Ottendorf-Okrilla, Germany

Ingolf Lorenz