Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Ingolf Frank

Xun Gong

Matthieu Chevrier

Lars Lotzenburger

Gerd Rombach

A gate drive adapter circuit includes an input circuit, an output circuit, and a charge pump circuit. The input circuit is configured to receive pulses suitable for controlling a silicon power transistor. The output circuit is coupled to the input circuit. The output circuit is configured to translate the pulses to voltages suitable for controlling a silicon-carbide power transistor. The charge pump circuit is coupled to the input circuit and to the output circuit. The charge pump circuit is configured to generate a negative voltage. The output circuit is configured to apply the negative voltage to translate the pulses.

Gate drive adapter

A system having a load that generates an EMF energy, comprising: a controller; a switch having a control terminal coupled to the controller and a second terminal coupled to the load; a recycling circuit coupled to the load and the second terminal of the switch, the recycling circuit including a capacitor and a converter coupled to the capacitor, a voltage source and the load; and wherein the capacitor is operable to store the EMF energy.

Bidirectional inverting buck-boost converter converting dissipation current into recycling current

A system to regulate power from a first power supply to a load coupled to the first power supply, wherein a power transistor is coupled between the load and ground. The system includes: a transistor having a control terminal, a first current terminal adapted to be coupled to an external second power supply and a second current terminal adapted to be coupled to a control terminal of the power transistor; a first resistor having a first node coupled to the control terminal of the transistor and a second node adapted to be coupled to a first terminal of a second external capacitor, the first node of the first resistor is adapted to be coupled to a first terminal of a first external capacitor; a second resistor having a first node coupled to the control terminal of the transistor and a second node adapted to be coupled to ground, the first node of the second resistor is adapted to be coupled to a first terminal of an first external resistor; and wherein a second terminal of the first external capacitor is coupled to a node between the load and a first current terminal of the power transistor and a second terminal of the second external capacitor is coupled to form a capacitive divider with the first external capacitor and the first resistor, and a second node of the first external resistor is coupled to the node between the load and the first current terminal of the power transistor to form a resistive divider with the second resistor.

Systems with power transistors, transistors coupled to the gates of the power transistors, and capacitive dividers coupled to the power transistors

An example system comprises: a power transistor comprising a gate, a first terminal, and a second terminal; a transistor comprising a gate, a first terminal, and a second terminal coupled to the gate of the power transistor; a capacitive divider coupled to the first terminal of the power transistor and the gate of the transistor; and a resistive divider coupled to the first terminal of the power transistor and the gate of the transistor.

In some examples, a device comprises a capacitor a bidirectional inverting buck-boost converter coupled to the capacitor and configured to couple to multiple loads and to a voltage source, wherein the bidirectional inverting buck-boost converter is configured to: compare a voltage across the capacitor with a reference voltage; and based on the comparison, facilitate converting a dissipation current flowing from one of the multiple loads into a recycling current.

The present disclosure provides a digital detector apparatus for use with a sensor unit is provided wherein the sensor unit includes an emitter device and a receiver device, the receiver device having a capacitance. The digital detector apparatus comprises at least a first input port, first output port, and a second output port; and an A/D converter circuit wherein an input of the A/D converter circuit is coupled to the first input port for receiving an output of the receiver device; wherein the first output port of the digital detector apparatus is coupled for charging and discharging the capacitance of the receiver device; the second output port of the digital detector apparatus is coupled for driving the emitter device; and the A/D converter circuit derives a sensor output value from the output of the receiver device during a number of charging and discharging cycles. A digital smoke detector and a method of generating an output signal in a digital detector are also provided.

Digital detector

A memory system is provided. In the system, there are first and second sets of dynamic random access memories (DRAMs) and a system register. Each DRAM has at least a first and a second addressable mode register, where the binary address of the second mode register is the inverted binary address of the first mode register. The system register has an input configured to be coupled to a controller, an output coupled to the first set of DRAMs via first address lines and an inverted output coupled to the second set of DRAMs via second address lines. The system register is configured to receive mode register set commands including address bits and configuration bits at the input and to output the mode register set commands non-inverted via the output to the first set of DRAMs and in inverted form via the inverted output to the second set of DRAMs.

Memory system and method for passing configuration commands

The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal, and a dynamic latch stage comprising an input transfer element, and a second bi-stable element coupled between the input transfer element and a dynamic latch data output, wherein the input transfer element is adapted to be switched by a second clock signal and a delayed second clock signal, which is delayed with respect to the second clock signal by a first period of time being shorter than half a period of the second clock signal, such that the input transfer element allows signal transfer only during the first period of time.

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Freising, Germany

Ingolf Frank