Infineon Technologies Ag

Qimonda Ag

Ingo Wennemuth

Jochen Thomas

Uta Gebauer

Minka Gospodinova-Daltcheva

Jens G Pohl

Harry Hedler

Wolfgang Hetzel

Anton Legen

Jürgen Högerl

Uta Sasse

Maksim Kuzmenka

Volker Strutz

Peter Weitz

Manuel Carmona

Juergen Grafe

Andreas W&ouml;rz

Hayri Burak Goekgoez

Harry Huebert

Rajesh Subraya

A semiconductor component () has an interposer substrate () as stack element of a semiconductor component stack (). The interposer substrate () has, on one of the interposer substrate sides (), a semiconductor chip protected by plastics composition () in its side edges (). An interposer structure () partly covered by a plastics composition () is arranged on the interposer side () opposite to the semiconductor chip (). Edge regions () of the interposer substrate () remain free of any plastics composition () and have, on both interposer sides () external contact pads () which are electrically connected to one another via through contacts ().

Semiconductor component comprising an interposer substrate

An electronic component includes a semiconductor chip with an active front face and a passive rear face, with contact connections and contact surfaces respectively being provided on the active front face and/or on the passive rear face, and with conductive connections being provided in the form of structured conductive tracks for providing an electrical connection from the active front face to the passive rear face. An electronic assembly formed of stacked semiconductor chips, and a method for producing the electronic component and the electronic assembly are also provided.

Electronic component with semiconductor chips, electronic assembly composed of stacked semiconductor chips, and methods for producing an electronic component and an electronic assembly

An integrated circuit provides a carrier substrate, a wiring level above a carrier substrate, wherein the wiring level comprises a first conductor track composed of a first conductive material and a second conductor track composed of the first conductive material, an insulating layer above the wiring level, wherein the insulating layer comprises a first opening in a region of the first conductor track of the wiring level and a second opening in a region of the second conductor track of the wiring level and a contact bridge composed of a second conductive material, wherein the contact bridge is connected to the first conductor track in a region of the first opening and is connected to the second conductor track in a region of the second opening.

Integrated circuit and method for producing the same

One aspect of the invention relates to a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition. Another aspect relates to a method for producing the same. The plastic housing composition has at least one host component having a softening temperature and an incorporated component having a phase change temperature. In this case, the softening temperature of the host component is greater than the phase change temperature of the incorporated component.

Semiconductor device comprising a housing and a semiconductor chip partly embedded in a plastic housing composition, and method for producing the same

A novel method and placement system are configured for populating a substrate with an electronic component. The placement system has a substrate holding device for receiving the substrate, a wafer holding device above the substrate holding device serving for receiving a wafer holding frame, and a vacuum forceps holding device arranged above the wafer holding device. The wafer holding frame can receive a complete semiconductor wafer divided into electronic components.

Placement system for populating a substrate with electronic components

A semiconductor device includes a plastic package, at least one semiconductor chip and a rewiring level. The rewiring level includes an insulating layer and a rewiring layer. The rewiring layer includes either signal conductor paths and ground or supply conductor paths arranged parallel to one another and alternately, or only signal conductor paths arranged parallel to one another. In the latter case, an electrically conducting layer of metal which can be connected to ground or supply potential is additionally provided as a termination of the rewiring level or in the form of a covering layer.

Semiconductor device with a rewiring level and method for producing the same

The invention relates to an electronic component having a multilayered rewiring plate, which carries a circuit chip, in particular a magnetic memory chip, and connects contact areas of the chip to external contacts of the electronic component via rewiring lines. The rewiring plate has at least one patterned, magnetic shielding layer made of an amorphous metal or an amorphous metal alloy. Furthermore, the invention encompasses a method for producing this electronic component.

Electronic component with multilayered rewiring plate and method for producing the same

A connecting element for electrically connecting a semiconductor chip and a superordinate circuit board includes an elastic metal strip that is bent forming two metal limbs with flattened limb ends, thus forming a base between the metal limbs which is suitable for contacting and providing electrical connectivity to a plurality of contact pads of a superordinate circuit board. At least one of the two limb ends is electrically connected to the contact areas of a semiconductor chip, while the other limb end is elastically supported on the top side of the semiconductor chip, thereby enabling the connecting element to be self supporting.

Self-supporting connecting element for a semiconductor chip

A method of stacking semiconductor chips includes providing four semiconductor chips that each include a top surface with central bond pads. Each of the bond pads is electrically coupled to second bond pads located in a peripheral portion of the semiconductor chip through a conductive layer. The first and the second semiconductor chips are arranged alongside one another on a carrier substrate. The second bond pads from the first and second semiconductor chips are bonded to corresponding landing pads on the substrate. The third semiconductor chip is then stacked over the first semiconductor chip and the fourth semiconductor chip over the second semiconductor chip. The second bond pads of the third and fourth semiconductor chips can then be bonded to contact pads of the substrate. The substrate can then be separated into a first stack that includes the first and third semiconductor chips and a second stack that includes the second and fourth semiconductor chips.

Method for manufacturing a stack arrangement of a memory module

Method for populating a substrate with electronic components

The invention relates to an FBGA arrangement, comprising a substrate on which at least one chip is chip-bonded face-down, which has a central row of bonding pads connected to contact islands (landing pads) on the substrate by a bonding channel in the substrate via wire bridges, which substrate, for its part, is provided with soldering balls&#x2014;arranged in an array&#x2014;for contact connection to a printed circuit board, and the contact islands and the soldering balls being connected to one another via a rewiring of the substrate. The preferred embodiment of the invention is intended to provide an FBGA arrangement which supports the center pad row technology and at the same time has low electrical parasitics. This is achieved by virtue of the fact that at least two substrates () are provided, the substrates () are provided substratewise in each case with bonding channels () having different dimensions, in a manner forming a multistage bonding channel, the bonding channels () in the ball-side substrate () having larger dimensions than those in the chip-side substrate ().

FBGA arrangement

A covering element for covering subassemblies having a substrate and at least one component disposed thereon and to be protected, in particular, a semiconductor component, includes at least one substantially planar area for covering the at least one component to be protected, one or more moldings serving for mechanical support, at least one of the moldings being in contact with the substrate and/or a supporting element disposed on the substrate after the covering element has been mounted on the subassembly, and the planar area and the molding being disposed such that, in the event of pressure on the covering element, no displacement of the at least one component () to be protected occurs.

Covering element for subassemblies

The electronic component has semiconductor chips that are stacked on one another. On their active top sides, the chips having interconnects for rewiring to contact areas through contacts formed on the sawn edges of the semiconductor chip. The electronic components of overlying and underlying semiconductor chips are thus connected to one another via the through contacts.

Method of fabricating an electronic component

An electronic component includes stacked electronic elements with external contacts. The external contacts are connected to contact terminal pads of an interconnect layer disposed on an isolating body. This isolating body extends over underlying side edges of a further electronic element, and its interconnect layer is connected to another interconnect layer of the stack via its external contact surfaces.

Growing community of inventors

Munich, Germany

Ingo Wennemuth