Intel Corporation

University of Utah Research Foundation

Intel IP Corporation

Jordaan Consulting Ltd. V, LLC

Ingo Wald

Carsten Benthin

Sven Woop

Johannes Guenther

Prasoonkumar Surti

Jefferson Amstutz

Gabor Liktor

Abhishek R Appu

Joydeep Ray

Altug Koker

Attila Afra

Carson Brownlee

Balaji Vembu

Subramaniam M Maiyuran

Murali Ramadoss

Guei-Yuan Lueh

Tomas G Akenine-Moller

David M Puffer

Brent E Insko

Elmoustapha Ould-Ahmed-Vall

Adam T Lake

Peter L Doyle

Daniel Pohl

Travis T Schluessler

Michael Apodaca

Ankur N Shah

Jacek Kwiatkowski

Robert M Toth

Aditya S Yanamandra

Santiago Ize

Peter Schuyler Shirley

Steven Parker

Attila Tamas Afra

Jörg Schmittler

Solomon Boulos

Philipp Slusallek

Gregory P Johnson

Aaron Knoll

A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.

Temporal data structures in a ray tracing architecture

An apparatus and method for efficient ray tracing. For example, one embodiment of an apparatus comprises: a general purpose processor to generate a plurality of ray streams; a first hardware queue to receive the ray streams generated by the general purpose processor; a graphics processing unit (GPU) comprising a plurality of execution units (EUs) to process the ray streams from the first hardware queue; a second hardware queue to store graphics processing jobs submitted by the GPU; the general purpose processor to process the jobs submitted by the GPU and share results with the GPU.

Apparatus and method for optimized ray tracing

Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

Apparatus and method for cross-instance front-to-back traversal for ray tracing heavily-instanced scenes

One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.

Page faulting and selective preemption

One embodiment provides a parallel processor comprising a memory interface and a processing array coupled with the memory interface. The processing array is configured to address memory accessed via the memory interface via a virtual address mapping and includes circuitry to resolve a page fault for the virtual address mapping, wherein each of the multiple compute blocks is separately preemptable.

One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.

Apparatus and method for foveated rendering, bin comparison and TBIMR memory-backed storage for virtual reality implementations

An apparatus and method are described for utilizing volume proxies. For example, one embodiment of an apparatus comprises: a volume subdivision module to subdivide a volume into a plurality of partitions, the apparatus to process a first of the partitions and to distribute data associated with each of the other partitions to each of a plurality of nodes; a proxy generation module to compute a first proxy for the first partition, the first proxy to be transmitted to the plurality of nodes; and a ray tracing engine to perform one or more traversal/intersection operations for a current ray or group of rays using the first proxy; if the ray or group of rays interacts with the first proxy, then the ray tracing engine to send the ray(s) to a second node associated with the first proxy or retrieves data related to the interaction from the second node.

Apparatus and method for data-parallel ray tracing using volume proxies

A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

Mechanism to accelerate graphics workloads in a multi-core computing architecture

Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.

Apparatus and method for compressing leaf nodes of a bounding volume hierarchy (BVH)

Apparatus and method for denoising of images generated by a rendering engine such as a ray tracing engine. For example, one embodiment of a system or apparatus comprises: A system comprising: a plurality of nodes to perform ray tracing operations; a dispatcher node to dispatch graphics work to the plurality of nodes, each node to perform ray tracing to render a region of an image frame; at least a first node of the plurality comprising: a ray-tracing renderer to perform ray tracing to render a first region of the image frame; and a denoiser to perform denoising of the first region using a combination of data associated with the first region and data associated with a region outside of the first region, at least some of the data associated with the region outside of the first region to be retrieved from at least one other node.

Apparatus and method for efficient distributed denoising of a graphics frame

An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.

Apparatus and method for hierarchical beam tracing and packet compression in a ray tracing system

Growing community of inventors

Salt Lake City, UT, United States of America

Ingo Wald