Infineon Technologies Dresden Gmbh & Co . Kg

Infineon Technologies Ag

Ingo Dirnstorfer

Erich Griebl

Matteo Dainese

Markus Beninger-Bina

Johannes Georg Laven

Caspar Leendertz

Frank Dieter Pfirsch

Christian Jaeger

Alexander Philippou

Hans-Joachim Schulze

Anton Mauder

Markus Bina

Christian Philipp Sandow

A power semiconductor device includes: first and second trenches extending from a surface of a semiconductor body along a vertical direction and laterally confining a mesa region along a first lateral direction; source and body regions in the mesa region electrically connected to a first load terminal; and a first insulation layer having a plurality of insulation blocks, two of which laterally confine a contact hole. The first load terminal extends into the contact hole to contact the source and body regions at the mesa region surface. A first insulation block laterally overlaps with the first trench. A second insulation block laterally overlaps with the second trench. The first insulation block has a first lateral concentration profile of a first implantation material of the source region along the first lateral direction that is different from a corresponding second lateral concentration profile for the second insulation block.

Power semiconductor device with p-contact and doped insulation blocks defining contact holes

A power semiconductor device includes: a semiconductor body; a control electrode at least partially on or inside the semiconductor body; elevated source regions in the semiconductor body adjacent to the control electrode; recessed body regions adjacent to the elevated source regions; and a dielectric layer arranged on a portion of a surface of the semiconductor body and defining a contact hole. The contact hole is at least partially filled with a conductive material establishing an electrical contact with at least a portion of the elevated source regions and at least a portion of the recessed body regions. At least one first contact surface between at least one elevated source region and the dielectric layer extends in a first horizontal plane. At least one second contact surface between at least one recessed body region and the dielectric layer extends in a second horizontal plane located vertically below the first horizontal plane.

Power semiconductor device having elevated source regions and recessed body regions

A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.

Power semiconductor switch having a cross-trench structure

A method of forming a power semiconductor device includes: arranging a control electrode at least partially on or inside a semiconductor body; forming elevated source regions in the semiconductor body by: implanting first conductivity type dopants into the semiconductor body; forming a recess mask layer covering at least areas of intended source regions; and removing portions of the semiconductor body uncovered by the recess mask layer to form the elevated source regions and recessed body regions at least partially between the source regions. A dielectric layer is formed on the semiconductor body. A contact hole mask layer is formed on the dielectric layer. Portions of the dielectric layer uncovered by the contact hole mask layer are removed to form a contact hole which is filled at least partially with a conductive material to establish an electrical contact with at least a portion of the elevated source and recessed body regions.

Method of forming a power semiconductor device

A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.

Power semiconductor device having a cross-trench arrangement

A method includes: forming trenches extending from a surface along a vertical direction into a semiconductor body, facing trench sidewalls of two adjacent trenches laterally confining a mesa region of the semiconductor body along a first lateral direction; forming a body region in the mesa region, a surface of the body region in the mesa region at least partially forming the semiconductor body surface; forming a first insulation layer on the semiconductor body surface; subjecting the semiconductor body region to a tilted source implantation using at least one contact hole in the first insulation layer at least partially as a mask for forming a semiconductor source region in the mesa region. The tilted source implantation is tilted from the vertical direction by an angle of at least 10&#xb0;. The semiconductor source region extends for no more than 80% of a width of the mesa region along the first lateral direction.

Power semiconductor device with reliably verifiable p-contact and method

A power semiconductor switch includes a cross-trench structure associated with at least one IGBT cell. The cross-trench structure merge at least one control trench, at least one dummy trench and at least one further trench of at least one IGBT cell to each other. The cross-trench structure overlaps at least partially along a vertical direction with trenches of the at least one IGBT-cell.

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Dresden, Germany

Ingo Dirnstorfer