Texas Instruments Corporation

Indumini W Ranmuthu

Shengyuan Li

Douglas Warren Dean

Priscilla Enid Escobar-Bowser

Echere Iroaga

Hong Jiang

Ashish Manjrekar

Mark A Wolfe

John Mitchell Perry

Manoj K Jain

Kenneth James Maggio

Craig Matthew Brannon

Brian Thomas Lynch

Reza Sharifi

Davy H Choi

Akihiko Doi

Marius Vicentiu Dina

Patrick Michael Teterud

Sami Kiriaki

Motomu Hashizume

Yuji Isobe

Roland Karl Son

Craig B Greenberg

Taisuke Kazama

Michael T Direnzo

Glenn C Mayfield

Mustapha El-markhi

Yong Han

Siang Tong Tan

Tracy S Paulsen

Yukihisa Hirotsugu

Axel Alegre De La Soujeole

Pavan Pakala

Ramlah Razak

Jinguji Naoko

Neel Seshan

Ashish Manjreka

Hae-Seok Cho

A voltage regulator control circuit includes a transistor input controller. The transistor input controller forces a slew control signal on its slew control output to a state responsive to a change in a load condition and forces an ON signal to a state on its first transistor control output. A first transistor has a first control input and first and second current terminals. A second transistor couples to the first transistor. A driver has a slew control input, a driver input, and a driver output. The driver input couples to the first transistor control output. The driver output couples to the first control input. Responsive to a first logic state of the slew control signal and a first state of the ON signal, the driver provides a higher current to the first control input, and responsive to a second state of the slew control signal and a first state of the ON signal, the driver provides a lower current to the first control input.

Reverse recovery protection in a switching voltage converter

A multi-port charging system includes a controller having a power input terminal coupled to a DC power output of a converter, multiple power output terminals coupled to the power input terminal, and a communications input terminal. The system includes multiple charger ports, the respective charger ports having a charging power line coupled to a respective one of the power output terminals, and a communications line coupled to the communications input terminal. The controller is configured to control the state of the control output terminal to set a voltage of the DC power output according to a selected highest common compatible voltage of one or more sink devices coupled to one or more respective ones of the charger ports.

Multiple output charging system and controller

A circuit includes a transistor, a first driver, a second driver, and a delay circuit. The transistor includes an array of transistor cells partitioned into a first switch and a second switch. The first driver is configured to control the first switch. The second driver is configured to control the second switch. The delay circuit is coupled between the first driver and the second driver. The delay circuit is configured to delay closure of the second switch until the first switch is closed and a voltage across the first switch is less than a predetermined voltage.

High-side transistor partitioning and control

An embodiment semiconductor structure includes a metal layer. The semiconductor structure also includes a redistribution layer (RDL) structure including an RDL platform and a plurality of RDL pillars disposed between the RDL platform and the metal layer. Additionally, the semiconductor structure includes an under-bump metal (UBM) layer disposed on the RDL platform and a solder bump disposed on the UBM layer, where the UBM layer, the RDL platform, and the RDL pillars form an electrical connection between the solder bump and the metal layer.

Semiconductor structure and method for wafer scale chip package

In some examples, a circuit includes a state machine. The state machine is configured to operate in a buck state in which the state machine is configured to control a power converter to operate in a buck mode of operation at a first frequency. The state machine is configured to determine that a switch time of the power converter has decreased to within a threshold amount of a minimum switch time for the power converter. The state machine is configured to, responsive to the switch time of the power converter having decreased to within the threshold amount of the minimum switch time for the power converter, transition from the buck state to a reduced frequency buck state in which the state machine is configured to control the power converter to operate in the buck mode of operation at a second frequency that is less than the first frequency.

Circuit electromagnetic interference control

Back-to-back power field-effect transistors with associated current sensors are disclosed. An example apparatus includes a first power field-effect transistor (FET) having a first source, and a second power FET having a second source. The first and second power FETs share a common drain. The first and second sources positioned on a first side of a substrate and the common drain positioned on a second side of the substrate opposite the first side. The example apparatus includes a current sensing FET positioned between a first portion of the first source of the first power FET and a second portion of the first source of the first power FET. The current sensing FET senses a current passing through the first and second power FETs.

Back-to-back power field-effect transistors with associated current sensors

A wafer test probe system, probe card, and method to test back-to-back connected first and second transistors of a wafer. The probe card includes a waveform generator circuit and probe needles to couple the waveform generator circuit to provide a first pulse signal of a first polarity using a body diode of the first transistor to test the second transistor, and to provide a second pulse signal of a second polarity using a body diode of the second transistor to the test the first transistor. One example includes a resistor connected between the waveform generator circuit and one of the probe needles. The probe card includes a probe needle to connect a sense transistor of the wafer to the first transistor during wafer probe testing.

Unclamped inductor switching test at wafer probe

A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (V) saturation condition and controls the first and second power FETs accordingly.

Linear switch circuits and methods

This disclosure describes techniques for controlling a power supply voltage for a high-side gate driver that is used in a power converter. In some examples, in response to an overvoltage condition that occurs on an input voltage lead of a power converter, a power converter may decouple a terminal of a charge pump capacitor from the input voltage lead, and couple the terminal of the capacitor to a reference voltage lead. In further examples, in response to an overvoltage condition that occurs on an input voltage lead of a power converter, a power converter may turn off both switching transistors.

Charge pump capacitor coupled to input, reference voltage for overvoltage

Techniques are described for integrating power field-effect transistors (FETs), pre-drivers, controllers, and/or resistors into a common multi-chip package for implementing multi-phase bridge circuits. The techniques may provide a multi-chip package with at least two high-side (HS) FETs and at least two low-side (LS) FETs, and place the at least two HS FETs or the at least LS FETs on a common die. Placing at least two FETs on a common die may reduce the number of die and the number of thermal pads (i.e., die pads) needed to implement a set of power FETs, thereby decreasing component count of a multi-phase bridge circuit and/or allowing a more compact, higher current density multi-phase bridge circuit to be obtained without significantly increasing thermal power dissipation of the circuit.

Power field-effect transistor (FET), pre-driver, controller, and sense resistor integration for multi-phase power applications

Circuit for controlling a power supply voltage for a high-side gate driver

Various apparatuses, methods and systems for damping a current driver are disclosed herein. For example, some embodiments provide an apparatus for supplying current, including an output transistor connected between a voltage supply and a current output, and an active clamp connected between the current output and a current sink. The active clamp is adapted to connect the current output to the current sink when a voltage at the current output reaches a predetermined state relative to a voltage at a control input of the output transistor.

Current driver damping circuit

An optical disk drive system associated with a laser diode is described. The optical disk drive system comprises a current generator for receiving input signals; a current switch coupled to receive timing signals; a current driver coupled to receive output signals from the current switch and the current generator, the current driver further comprising a driver with wave shape control selected from the group consisting of a laser diode read driver and a laser diode write driver, wherein the driver with shape control is operative for transmitting at least one output signal that is a scaled version of at least one of the output signals received from the current generator, wherein the current driver is operative for transmitting at least one output signal driving the laser diode.

Laser diode driver with wave-shape control

Laser diode write driver feedback, current mirror, and differential-pair circuitry

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Plano, TX, United States of America

Indumini W Ranmuthu