Purdue Research Foundation

Intel Corporation

Indranil Chakraborty

Kaushik Roy

Amogh Agrawal

Tanay Karnik

Akhilesh Ramlaut Jaiswal

Ranganath Krishnan

Srivatsa Rangachar Srinivasa

Jainaveen Sundaram Priya

Aayush Ankit

Utkarsh Saxena

Dileep Kurian

Mustafa Fayez Ahmed Ali

Methods, apparatus, systems, and articles of manufacture providing a Bayesian compute unit with reconfigurable sampler and methods and apparatus to operate the same are disclosed. An example apparatus includes a number generator to generate a sequence of numbers; a multiplier to generate a plurality of products by multiplying respective numbers of the sequence of the numbers by a variance value; and an adder to generate a plurality of weights by adding a mean value to the plurality of products, the plurality of weights corresponding to a single probability distribution.

Bayesian compute unit with reconfigurable sampler and methods and apparatus to operate the same

Sparsity-aware reconfiguration compute-in-memory (CIM) static random access memory (SRAM) systems are disclosed. In one aspect, a reconfigurable precision succession approximation register (SAR) analog-to-digital converter (ADC) that has the ability to form (n+m) bit precision using n-bit and m-bit sub-ADCs is provided. By controlling which sub-ADCs are used based on data sparsity, precision may be maintained as needed while providing a more energy efficient design.

Sparsity-aware reconfigurable compute-in-memory (CIM) static random access memory (SRAM)

A method of obtaining an in-memory vector-based dot product is disclosed, which includes providing a matrix of memory cells having M rows, each memory cell in each row holding a value and having dedicated read transistors Tand T, where Tis controlled by the value held in the associated memory cell and Tis controlled by a row-dedicated source (v) for each row, the combination of the Tand Ttransistors for each cell selectively (i) couple a reference voltage with a column-dedicated read bit line (RBL) for each column for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column for a memory read operation, where total resistance of the read transistors (R) for each cell in each row is based on Rmax/2, . . . Rmax, where Rmax is the resistance of the least significant cell in each row.

Multi-bit dot product engine

Growing community of inventors

West Lafayette, IN, United States of America

Indranil Chakraborty