Advanced Micro Devices Corporation

Ati Technologies Ulc

Dell Products Inc.

Indrani Paul

Manish Arora

Alexander J Branover

Benjamin Tsien

John P Petry

Mihir Shaileshbhai Doctor

Thomas James Gibney

Christopher T Weaver

Leonardo De Paula Rosa Piga

Stephen Victor Kosonocky

Wei T Huang

Sriram Sambamurthy

Dana Glenn Lewis

Wonje Choi

Leonardo Piga

Timothy Michael Lambert

Larry David Hewitt

Yasuko Eckert

Karthik Rao

Aaron Joseph Grenat

Samuel D Naffziger

Kevin Michael Lepak

Srilatha Manne

Steven Frederick Liepe

William Lloyd Bircher

Adam Neil Calder Clark

Sandhya Shyamasundar

Mukund Purshottam Khatri

Nuwan S Jayasena

Johan Rahardjo

John S Loffink

Anil Harwani

Oleksandr Khodorkovsky

Oswin Hall

Dennis Au

Adam N C Clark

Sriram Sundaram

Abhinandan Majumdar

Donny Yi

Vignesh Trichy Ravi

Sandor Tibor Farkas

James Raymond Magro

Joseph Lee Greathouse

Kevin M Brandl

Bhavesh Govindbhai Patel

Chintan S Patel

Mitesh Ramesh Meswani

Rathijit Sen

Michael J Austin

Madhu Saravana Sibi Govindan

Dong Ping Zhang

Pravesh Gupta

Aubrey K Sparkman

Yazhou Zu

Darrell J Slupek

Xinzhe Li

Ashwini Chandrashekhara Holla

Sukesh Shenoy

Jean J Chittilappilly

Samuel Lawrence Wasmundt

Mahesh Subramony

Brian J Kocoloski

Can Hankendi

Kenneth Mitchell

Akanksha Jain

Sonu Arora

David James Roberts

Abhishek Kumar Verma

Meeta Surendramohan Srivastav

Alex Sabino Duenas

Ivan Matosevic

Jose G Cruz

Donald Cherepacha

Md Abdullah Shahneous Bari

Peter Bailey

Hector F Martinez

Larry P Robison, Jr

Kavyashree Pilar

Wei Huang

A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

Operating voltage adjustment for aging circuits

Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

Platform power manager for rack level power and thermal constraints

Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.

On-demand IP initialization within power states

Devices and methods for cache prefetching are provided. A device is provided which comprises a quality of service (QOS) component having first assigned registers used to store data to execute a program, a plurality of non-QOS components having second assigned registers used to store data to execute the program and a power management controller, in communication with the QOS component and the non-QOS components. The power management controller is configured to issue fences for the non-QOS components when it is determined that one or more of the non-QOS components are idle, issue a fence for the QOS component when the fences for the non-QOS components are completed and enter a reduced power state when the fences for the non-QOS components and the fence for the QOS component are completed.

Device and method for two-stage transitioning between reduced power states

A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.

Method and apparatus for managing power states

An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.

Low power state selection based on idle duration history

A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.

Technique for extended idle duration for display to improve power consumption

A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.

Device and method for efficient transitioning to and from reduced power state

Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.

Using a hardware-based controller for power state management

A method and apparatus for managing a controller includes indicating, by a processor of a first device, to the controller of a second device to enter a second power state from a first power state. The controller of the second device responds to the processor of the first device with a confirmation. The processor of the first device transmits a signal to the controller of the second device to enter the second power state. Upon receiving a wake event, the controller of the second device exits the second device from the second power state to the first power state.

Method and apparatus for managing a controller in a power down state

Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on an integrated circuit (IC), and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.

Method and apparatus for providing non-compute unit power control in integrated circuits

Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.

Device and method for reducing save-restore latency using address linearization

A processing unit of a processing system compiles a priority queue listing of a plurality of processor cores to run a workload based on a cost of running the workload on each of the processor cores. The cost is based on at least one of a system usage policy, characteristics of the workload, and one or more physical constraints of each processor core. The processing unit selects a processor core based on the cost to run the workload and communicates an identifier of the selected processor core to an operating system of the processing system.

Core selection based on usage policy and core constraints

An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.

Distributing power shared between an accelerated processing unit and a discrete graphics processing unit

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Round Rock, TX, United States of America

Indrani Paul