Intel Corporation

Indraneel Ghosh

Thomas A Piazza

Val Gene Cook

Kim A Meinerth

David W Watson

Eric C Samson

Sam W Jensen

Subeer Kamal Patel

Chin Shu Tan

Wenteh Pan

Srinivasu Pappula

Aditva Sreerivas

A configurable filter module for providing shared filter resource between an overlay engine and a texture mapping engine of a graphics system. The configurable filter may comprise a plurality of linear blend units each of which receives data input from one of the overlay engine and a mapping engine cache, and generates a linear blend filter output respectively; and a filter output multiplexer which receives data output from the linear blend units and selects a proper byte ordering output, wherein the linear blend units serve as an overlay interpolator filter to perform linear blending of the data input from the overlay engine during a linear blend mode, and serve as a texture bilinear filter to perform bilinear filtering of the data input from the mapping engine cache during a bilinear filtering mode.

Pixel filtering using shared filter resource between overlay and texture mapping engines

Method and apparatus for pixel filtering using shared filter resource between overlay and texture mapping engines

A method, apparatus and system for storing data wherein pieces of data are selectively combined at times when a storage device is not able to accept requests to store data for a duration sufficient that multiple additional pieces of data have been received since the last request to store data was made and at least two of those pieces of data are able to be combined into a piece of data that is better configured for storage.

System and method for increasing the efficiency and reliability of the storage of sequential data

A data storage device is provided. The data storage device, which is coupled to a data processing device, includes a memory array partitioning into a plurality of memory banks. The data storage device further includes a bank enable circuit for enabling at least one of the memory banks from the plurality of memory banks of the memory array. The data storage device also includes an operation/pseudooperation enable circuit (OPEC) for generating an operation or a pseudooperation signal to one or more banks enabled by the bank enable circuit. The OPEC has a first input for receiving an operation request signal from the data processing device and a second input. Additionally the data storage device includes a pseudooperation control circuit for controllably generating a pseudooperation request signal to the bank enable circuit and to the second input of the OPEC.

Banked SRAM device with bit line refresh

Growing community of inventors

Sunnyvale, CA, United States of America

Indraneel Ghosh