Chartered Semiconductor Manufacturing Ltd (corporation)

Agilent Technologies, Inc.

Globalfoundries Singapore Pte. Ltd.

Indrajit Manna

Lo Keng Foo

Keng Foo Lo

Raymond A Filippi

Pee Ya Tan

Tan Pee Ya

Michael Cheng

Jae Soo Park

Hin Kiong Yap

Zeng Xu

Guo Qiang

A tunable protection system including forming a tunable trigger device providing an adjustable protection activation level, forming a circuit protection device providing protection for integrated circuits, and electrically connecting the tunable trigger device and the circuit protection device to an input/output pad.

Tunable protection system for integrated circuits

An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Triggered silicon controlled rectifier for RF ESD protection

An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Method for forming an ESD protection circuit

Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

Electrostatic discharge protection device with complementary dual drain implant

A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.

ESD protection device

A ring oscillator circuit device is achieved. The device comprises an odd number of inverting stages. Each inverting stage has an input terminal and an output terminal. The inverter stages are coupled in a ring such that the output terminals of preceding inverting stages are coupled to the input terminals of subsequent inverting stages. A variable capacitor is included. The variable capacitor comprises a conductive layer overlying a bulk semiconductor region with a dielectric layer therebetween. The conductive layer is coupled to the output terminal of one of the inverting stages. The value of the variable capacitor depends on a bulk voltage that is coupled to the bulk semiconductor region. The ring oscillator is used for analyzing load dependence of hot carrier injection. The ring oscillator is used as a voltage-controlled oscillator in a phase-locked loop circuit.

Ring oscillator with variable loading

A first on-chip test structure monitors hot carrier degradation. A degrading ring oscillator is subjected to hot carrier effects while a non-degrading ring oscillator is not. As the device ages, hot carrier effects degrade the degrading ring counter. The second test structure monitors TDDB degradation. A plurality of N parallel connected capacitors have a stress voltage applied to them such that the time to failure of the first capacitor is the same that experienced by percentage of gates under normal usage. A drop in the resistance indicates breakdown of a capacitor. The third test structure monitors electromigration degradation. M minimum width metal lines are connected in parallel. A current is applied such that the time to failure of all metal lines is the same as that experienced by a percentage of minimum width metal lines under normal usage. An increase in resistance indicates breakdown of a metal line.

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Singapore, Singapore

Indrajit Manna