Intel Corporation

Daedalus Prime LLC

Other

Tahoe Research, Ltd.

Daedauls Prime LLC

Inder M Sodhi

Ryan Donovan Wells

Sanjeev S Jahagirdar

Doron Rajwan

Varghese George

Alon Naveh

Zeev Offen

Eliezer Weissmann

Ashish V Choubal

Nadav Shulman

Ken Drottar

Itai Feit

Efraim Rotem

Stephen H Gunther

Satish K Damaraju

Rabiul Islam

Vishram Sarurkar

Yun-Han Chen

Avinash N Ananthakrishnan

Dheeraj R Subbareddy

Eugene Gorbatov

David A Koufaty

Ganapati Srinivasa

Paolo L Narvaez

Mishali Naik

Joydeep Ray

Andrew J Herdrich

Eric C Samson

Jeremy J Shrall

Russell Jerome Fenger

Andrew D Henroid

Scott D Hahn

Gaurav Khanna

Paul Brett

Abirami Prabhakaran

Jason W Brandt

Michael Mishaeli

Jeffrey R Wilcox

Nicholas J Adams

Daniel J Ragland

Tanveer R Khondker

Bret L Toll

Krishnakanth Venkata Sistla

Ravishankar Iyer

Ankush Varma

Stephen Anthony Fischer

Vivek Garg

James Steven Burns

Hisham Shafi

Rinat Rappoport

Martin Rowland

Nagabhushan Chitlur

Yair Talker

Inbar Falkov

Tapan A Ganpule

Oron Lenz

Kedar Mangrulkar

Venkatesh Prasanna

Cesar A Quiroz

Sanjeev S Sahagirdar

Paul S Diefenbaugh

Barnes Cooper

Nikos Kaburlasos

Christopher P Mozak

Michael Zelikson

Shaun M Conrad

Faraz A Siddiqi

Philip R Lehwalder

Xiuting C Man

John B Conrad

Marc D Torrant

Mathew B Nazareth

Michael Calyer

Vijay K Vuppaladadium

Amjad M Khan

Ruchika Singh

Shalini Sharma

Eliezer Wiessman

Sanjeev S Jahagirdhar

Uzi Sasson

Mark A Newman

Tanjeer R Khondker

Miguel Corvacho

Nakul Arora

Ryan D Wells

Russel J Fenger

Guarav Khanna

Jeffery L Krieger

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

Controlling operating voltage of a processor

Controlling operating frequency of a processor

In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.

Controlling power delivery to a processor via a bypass

Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices

A processor includes a first memory interface to be coupled to a plurality of memory module sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the memory modules disposed in the plurality of memory module sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power memory module disposed in one of the memory module sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power memory module as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.

Common platform for one-level memory architecture and two-level memory architecture

According to one embodiment of the invention, a processor includes a power control unit, an interface to software during runtime that permits the software to set a plurality of power management constraint parameters for the power control unit during runtime of the processor without a reboot of the processor, and a storage element to store a respective lock bit for each of the plurality of power management constraint parameters to disable the interface from changing a respective constraint parameter when set.

System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time

Some implementations provide techniques and arrangements to migrate threads from a first core of a processor to a second core of the processor. For example, some implementations may identify one or more threads scheduled for execution at a processor. The processor may include a plurality of cores, including a first core having a first characteristic and a second core have a second characteristic that is different than the first characteristic. Execution of the one or more threads by the first core may be initiated. A determination may be made whether to apply a migration policy. In response to determining to apply the migration policy, migration of the one or more threads from the first core to the second core may be initiated.

Migrating threads between asymmetric cores in a multiple core processor

In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

Enabling a non-core domain to control memory bandwidth in a processor

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Method for booting a heterogeneous system and presenting a symmetric core view

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Folsom, CA, United States of America

Inder M Sodhi