Samsung Electronics Co., Ltd.

Inchan Hwang

Hwichan Jun

Byounghak Hong

Heonjong Shin

Doohyun Lee

Sunghun Jung

Seunghyun Song

Kyungin Choi

Changhwa Kim

Minchan Gwak

Hyunho Park

Yongsik Jeong

Sangwon Jee

Hakyoon Ahn

Kang Ill Seo

Joon-Gon Lee

Chang-Hwa Kim

A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.

Semiconductor device

A stacked semiconductor device includes: a substrate; a 1transistor formed on a substrate, and including a 1active region surrounded by a 1gate structure and 1source/drain regions; and a 2transistor stacked on the 1transistor, and including a 2active region surrounded by a 2gate structure and 2source/drain regions, wherein the 1active region and the 1gate structure are vertically mirror-symmetric to the 2active region and the 2gate structure, respectively, with respect to a virtual plane therebetween.

Stacked semiconductor device having mirror-symmetric pattern

A semiconductor device includes a substrate; a 1transistor formed above the substrate, and having a 1transistor stack including a plurality of 1channel structures, a 1gate structure surrounding the 1channel structures, and 1and 2source/drain regions at both ends of the 1transistor stack in a 1channel length direction; and a 2transistor formed above the 1transistor in a vertical direction, and having a 2transistor stack including a plurality of 2channel structures, a 2gate structure surrounding the 2channel structures, and 3and 4source/drain regions at both ends of the 2transistor stack in a 2channel length direction, wherein the 3source/drain region does not vertically overlap the 1source/drain region or the 2source/drain region, and the 4source/drain region does not vertically overlap the 1source/drain region or the 2source/drain region.

Crossing multi-stack nanosheet structure and method of manufacturing the same

Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate and may include a conductive contact. The upper transistor may include an upper source/drain region that overlaps a lower source/drain region of the lower transistor. The conductive contact may contact a side surface of the upper source/drain region and may overlap a center portion of the lower source/drain region. The side surface of the upper source/drain region may include a protrusion and a recess.

Integrated circuit devices including stacked transistors

A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.

Semiconductor device having silicides and methods of manufacturing the same

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a static random access memory (SRAM) including a plurality of transistors disposed in a first layer and a second layer. The first layer includes a first shared gate of a first transistor and a second shared gate of a second transistor, among the plurality of transistors. The second layer is disposed above the first layer and includes a third shared gate of a third transistor and a fourth shared gate of a fourth transistor, among the plurality of transistors. The third shared gate is disposed above the first shared gate, and the fourth shared gate is disposed above the second shared gate. The SRAM further includes a first shared contact, a second shared contact, a first cross-couple contact connecting the fourth shared gate and the first shared contact, and a second cross-couple contact connecting the third shared gate and the second shared contact.

Static random access memory of 3D stacked devices

A semiconductor device include: a substrate; a 1transistor formed above the substrate, the 1transistor including a 1channel set of a plurality of 1nanosheet layers, a 1gate structure surrounding the 1nanosheet layers, and 1and 2source/drain regions at both ends of the 1channel set; and a 2transistor formed above the 1transistor in a vertical direction, the 2transistor including a 2channel set of a plurality of 2nanosheet layers, a 2gate structure surrounding the 2nanosheet layers, and 3and 4source/drain regions at both ends of the 2channel set, wherein the 1channel set has a greater width than the 2channel set, wherein a number of the 1nanosheet layers is smaller than a number of the 2nanosheet layers, and wherein a sum of effective channel widths of the 1nanosheet layers is substantially equal to a sum of effective channel width of the 2nanosheet layers.

Semiconductor device having stepped multi-stack transistor structure

An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.

Array of multi-stack nanosheet structures

An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.

Integrated circuit device

A semiconductor device includes a substrate with lower structures, an insulation layer covering the lower structures on the substrate, a contact hole through the insulation layer partially exposing the substrate, and a contact structure contacting the substrate through the contact hole, the contact structure including a barrier pattern having an upper barrier on an upper portion of a sidewall of the contact hole, and a lower barrier filling a lower portion of the contact hole, and a conductive contact pattern filling an upper portion of the contact hole defined by the upper barrier and the lower barrier.

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Siheung-si, South Korea

Inchan Hwang