Samsung Electronics Co., Ltd.

In-Wook Oh

Jong-Hyun Lee

Sung-Wook Hwang

Donghyun Kim

Jae-Seok Yang

HyunJae Lee

Sunhom Steve Paak

Jaeseok Yang

Nam-su Lim

Chin Woo Kim

Jong-sun Sel

Byungyun Kang

Hyungjune Kim

Jaebong Jung

Disclosed is a semiconductor device comprising a substrate that includes a cell region and a dummy region, a first metal layer on the substrate and including a dummy line on the dummy region, a power delivery network on a bottom surface of the substrate, and a first through via that penetrates the substrate and extends from the power delivery network toward the dummy line. The first through via is electrically connected to the dummy line. The power delivery network includes a plurality of lower lines and a pad line below the lower lines. The pad line is electrically connected through the lower lines to the first through via.

Semiconductor device

A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.

Wiring structure and method of forming a wiring structure

Provided is a semiconductor device. The device includes a plurality of line patterns, which extend in a first direction and are arranged a first space apart from one another in a second direction perpendicular to the first direction. The line patterns include a line pattern set including two sub-line patterns that are arranged the first space apart from each other in the second direction and have a first width of a minimum feature size (1F) in the second direction, and a wide-width line pattern that is arranged the first space apart from one side of the line pattern set in the second direction and has a second width larger than the first width in the second direction.

Semiconductor device including line patterns

A method of fabricating a semiconductor device includes providing a substrate that includes first and second main regions and a dummy region, and forming dummy active patterns on the dummy region. The first and second main regions are spaced apart from each other in a first direction and the dummy region includes a dummy connection region between the first and second main regions and first and second dummy cell regions spaced apart from each other in a second direction. First dummy active patterns, second dummy active patterns, and connection dummy active patterns connecting some of the first dummy active patterns to some of the second dummy active patterns are provided on the first and second dummy cell regions and the dummy connection region, respectively.

Methods of fabricating a semiconductor device

A test system includes row decoder, column decoder, row test controller, and test circuit. The row decoder activates one of first through M-th row signals based on plurality of row input signals. The column decoder activates one of first through N-th column signals based on plurality of column input signals. The row test controller outputs first through N-th column output signals, which are activated, when row test enable signal is activated. The row test controller outputs the first through N-th column signals as the first through N-th column output signals respectively when the row test enable signal is deactivated. The test circuit includes first through M-th row test blocks, each of which includes first through N-th test units. The test circuit simultaneously performs short test of the first through N-th test units included in row test block when the row test enable signal is activated.

Test system that performs simultaneous tests of multiple test units

A semiconductor device or a memory which includes the same have a line pattern, and a contact plug, the line pattern including a first linear feature to which the contact plug is connected by design, and a second linear feature having a connecting portion and a dummy portion adjacent the location at which the contact plug is electrically connected to the first linear feature. A second contact plug is electrically connected to the connecting portion of the second linear feature of the line pattern. In the case of a misalignment error or the like, the first contact plug may also be electrically connected to the second linear feature of the line pattern but at the dummy portion thereof so as to not create a short circuit in that case. The dummy portion thus allows a sufficiently large process margin to be secured for the contact plug.

Growing community of inventors

Suwon-si, South Korea

In-Wook Oh