Samsung Electronics Co., Ltd.

In-Woo Jun

Sang-Uhn Cha

Ye-Sin Ryu

Hoon Sin

Hyun-Gi Kim

Min Soo Kim

Myeong-O Kim

Won-Chang Jung

Byung Hoon Jeong

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices

A memory device including: a memory cell array; a first data input/output pin through which a first signal is input or output, wherein the first signal includes first bits to be written in the memory cell array or output from the memory cell array; a second data input/output pin through which a second signal is input or output, wherein the second signal includes second bits to be written in the memory cell array or output from the memory cell array; a first receiver configured to receive first operation codes for the first signal through the first data input/output pin; a second receiver configured to receive second operation codes for the second signal through the second data input/output pin; a first mode register configured to store the first operation codes; and a second mode register configured to store the second operation codes.

Memory device for receiving operation codes through dq pins, a memory module including the same, and a setting method of the memory module

Semiconductor semiconductor memory devices, memory systems and methods of operating memory devices

A memory device is configured to perform a parallel read-modify-write operation, which generates a syndrome for first partial data read from a memory cell array and second partial data according to a data mask option, corrects an error of the second partial data, generates merged data by combining second data with the corrected second partial data, and generates an internal parity for the merged data. The memory device sets the second partial data to binary values of 0, generates third data by combining the second partial data set to the binary values of 0 with the second data, generates a third parity for the third data, and generates an internal parity for the merged data based on the syndrome, a partial parity, and the third parity.

Memory device for performing parallel read-modify-write operation

Semiconductor memory device may include a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The control logic circuit may, in a first write operation mode, control the I/O gating circuit to select a sub-page, read a first unit of data including a first sub unit of data, a second sub unit of data and a first parity data from the sub-page, and provide the first unit of data to the error correction circuit. The control logic circuit may also control the error correction circuit to perform an error-correcting code decoding on the first unit of data to generate syndrome data, generate second parity data based on a portion of the first unit of data and generate third parity data based on a write parity data, the second parity data and the syndrome data.

A local sense amplifier circuit in a semiconductor memory device, the local sense amplifier circuit including a local data sensing unit configured to amplify a voltage difference between a local input/output (I/O) line pair based on a local sensing enable signal to provide the amplified voltage difference to a global I/O line pair, the local I/O line pair including a first local I/O line and a second local I/O line, and a local I/O line control unit including a first capacitor and a second capacitor, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal.

Local sense amplifier circuit and semiconductor memory device including the same

A latency circuit comprises a latency control block, an internal read command generator, and a latency signal generation unit. The latency control block generates a plurality of first control clocks by delaying a delay sync signal generated based on an external clock, and generates a second control clock having a margin with respect to a read command decoded based on the delay sync signal. The internal read command generator samples the second control clock using the decoded read command and generates an internal read command based on a sampled second control clock. The latency signal generation unit generates a latency signal based on a shifting operation performed on the internal read command using the plurality of first control clocks.

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Hwaseong-si, South Korea

In-Woo Jun