Skhynix Inc.

In Sung Koh

Sang Kwon Lee

A data sorting control circuit includes a phase detector suitable for detecting a phase of each of a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal in response to a read command, an order determiner suitable for determining a data order as a first order or a second order based on a seed address and the detected phase of each of the clock signals, and an sorting control signal generator suitable for shifting the read command based on the first clock signal to the fourth clock signal to generate a first sorting control signal, a second sorting control signal, a third sorting control signal, and a fourth sorting control signal, and outputting the first sorting control signal to the fourth sorting control signal according to the first order or the second order.

Data sorting control circuit and memory device including the same

An electronic system includes a controller configured to output a clock, a command, and an address, and configured to receive and transmit data. The electronic system also includes a semiconductor device including an error calculation circuit. The semiconductor device is configured to generate, by the error calculation circuit, a parity including information on an error included in transfer data generated from the data, in a write operation initiated by the command, and to generate, by the error calculation circuit, a syndrome including information on an error included in transfer data generated from internal data, in a read operation initiated by the command.

Electronic system including error calculation circuit for performing error correction operation

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs command/address signals and a plurality of data. The second semiconductor device generates a first mode signal and a second mode signal according to a combination of the command/address signals. The second semiconductor device is suitable for inverting the plurality of data inputted through a pad in response to the first or the second mode signal to store the inverted data suitable for blocking input of the inverted data in response to the second mode signal if a number of bits having a predetermined level in the plurality of data is equal to or greater than a predetermined number.

Semiconductor devices and semiconductor systems including the same

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs command/address signals, data and a test mode signal. The first semiconductor device receives output data from the second semiconductor device. The second semiconductor device buffers the data inputted through a first pad to write the buffered data according to a combination of the command/address signals or inversely buffers the data to write the inversely buffered data if a control signal enabled in response to the test mode signal inputted through a second pad is inputted through a third pad.

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Anyang-si, South Korea

In Sung Koh