Samsung Electronics Co., Ltd.

In-Sun Park

Hyeon-Deok Lee

Jong-myeong Lee

Ju-Cheol Shin

Jong-Won Hong

Hyun-Seok Lim

Hei-seung Kim

Hyun-Suk Lee

Gyu-Hwan Oh

Eung-Joon Lee

Young-Cheon Kim

Gil-heyun Choi

Hyun-young Kim

Ji-soon Park

Hyun-seok Lim

Shin-Jae Kang

Rak-Hwan Kim

Nak-Hyun Lim

Hong-Mi Park

Jong-Sik Chun

Do-Hyung Kim

Jong-Myeong Lee

Won-sang Song

Young-Joo Cho

Kwan-Jong Roh

Dong-Jo Kang

Ji-Soon Park

Kyoung-Hee Nam

Byung-Hee Kim

Sung-Tae Kim

Byeong-Chan Lee

In-gyu Baek

Sang-Bom Kang

Sang-Min Lee

Ki-Vin Im

Jong-Min Baek

Jae-Young Park

Byoung-Moon Yoon

Jung-hee Chung

Yong-Woo Hyung

Jeong-Hwan Yang

Bulliard Xavier

Won-Jun Jang

Soo-Ghang Ihn

Su-Kyoung Kim

Woo-bin Song

Sang-bum Kang

Ki-Jong Lee

Dae-Joung Kim

Jung-Wook Kim

Kyung-Bum Koo

Jung-soo Yoon

Sung-young Yun

Yeong-Suk Choi

Heung-Kyu Park

Seong-geon Park

Youn-Hee Lim

Se-jun Oh

Yeon-Ji Chung

Young-Tae Ma

Hyun-Deok Lee

In-Su Ha

Jong-sik Chun

Hong-mi Park

Chul Whang-Bo

A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

Semiconductor devices and methods of manufacturing the same

A polymer, and an organic solar cell including the polymer, include a repeating unit A represented by Chemical Formula 1, and a repeating unit B represented by Chemical Formula 2.

Electron donating polymer and organic solar cell including the same

A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.

Method of fabricating semiconductor device

According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.

Method of forming micropattern, method of forming damascene metallization, and semiconductor device and semiconductor memory device fabricated using the same

A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.

Non-volatile memory devices having resistance changeable elements and related systems and methods

A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.

Non-volatile memory device

Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

Semiconductor device conductive pattern structures including dummy conductive patterns

An interconnection structure having an oxygen trap pattern in a semiconductor device, and a method of fabricating the same are provided. The interconnection structure includes a lower interlayer insulating layer formed on a semiconductor substrate. A metal layer pattern and a capping layer pattern are sequentially stacked on the lower interlayer insulating layer. An oxygen trap pattern is disposed on the capping layer pattern and includes a conductive oxygen trap pattern.

Interconnection structure having oxygen trap pattern in semiconductor device

The present invention provides methods of forming a phase-change material layer including providing a substrate and a chalcogenide target including germanium (Ge), antimony (Sb) and tellurium (Te) at a temperature wherein tellurium is volatilized and antimony is not volatilized, and performing a sputtering process to form the phase-change material layer including a chalcogenide material on the substrate. Methods of manufacturing a phase-change memory device using the same are also provided.

Methods of forming a phase-change material layer including tellurium and methods of manufacturing a phase-change memory device using the same

Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming an ohmic layer on an upper surface of a conductive structure and extending away from the structure along at least a portion of a sidewall of an opening in an insulation layer. An electrode layer is formed on the ohmic layer. A variable resistivity material is formed on the insulation layer and electrically connected to the electrode layer.

Variable resistance non-volatile memory cells and methods of fabricating same

A phase change memory device includes a current restrictive element interposed between an electrically conductive element and a phase change material. The current restrictive element includes a plurality of overlapping film patterns, each of which having a respective first portion proximal to the conductive element and a second portion proximal to the phase change material. The second portions are configured and dimensioned to have higher resistance than the first portions.

Phase change memory device and method of forming the same

In an embodiment, a storage electrode of a capacitor in a semiconductor device is resistant to inadvertent etching during its manufacturing processes. A method of forming the storage electrode of the capacitor is described. The storage electrode of the capacitor may include a first metal layer electrically connected with a source region of a transistor through a contact plug penetrating an insulating layer on a semiconductor substrate. A polysilicon layer may then be formed on the first metal layer. A second metal layer is formed on the polysilicon layer.

Storage electrode of a capacitor and a method of forming the same

A semiconductor device is formed by forming a gate region, including a gate oxide layer, and impurity diffusion regions on a semiconductor substrate, forming a barrier metal layer on the gate region and the impurity diffusion regions of the semiconductor substrate, forming a passivation layer at an interface between the semiconductor substrate and the gate oxide layer to remove defects of the gate oxide layer, and then performing a nitridation process to remove impurities from the semiconductor substrate.

Methods of fabricating a semiconductor device having a barrier metal layer and devices formed thereby

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Seoul, South Korea

In-Sun Park