Samsung Electronics Co., Ltd.

In-su Yang

Ho-sun Yoo

Jae-il Lee

Sung-Yeol Kim

In-ho Choi

Woon-sup Choi

Chul-woong Jang

Min Sung Kim

Jin-Kyu Choi

Sung Yeol Kim

Ho Sun Yoo

Seung-ho Jang

Jong-pill Park

Jeong-Gon Lee

Jae Hyun Baek

Min-sung Kim

Young-ki Kwak

Seung-jun Chee

A semiconductor test system includes a user device configured to operate a reference device in accordance with an interface signal based on a timing signal having a variable operating frequency, a pattern synthesis apparatus configured to measure an interval between adjacent edges of the timing signal transmitted from the user device, and extract a logic value of the interface signal in accordance with the timing signal so as to generate test pattern data, and a test device configured to receive the test pattern data, reconstruct the timing signal based on the measured interval, generate a test driving signal such that the logic value is extracted from a device under test (DUT) based on the reconstructed timing signal, and apply the test driving signal to the DUT so as to determine an operating state of the DUT.

Pattern synthesis apparatus and semiconductor test system having the same

A signal capture system for capturing a signal and storing the captured signal in a storage apparatus in real time, and a test apparatus including the signal capture system. The signal capture system includes a printed circuit board; a socket that is connected to the printed circuit board and on which a reference memory component is mounted; and an interposer that is mounted on the printed circuit board, is connected to the socket, an external apparatus, and a storage apparatus, receives first signals from the reference memory component and transmits the received first signals to the external apparatus and the storage apparatus, and receives second signals from the external apparatus and transmits the received second signals to the reference memory component and the storage apparatus, wherein a shape of the socket is defined according to a type of the reference memory component.

Signal capture system and test apparatus including the same

A field mounting-type test apparatus and method for enhancing competitiveness of a product by simulating various test conditions including a mounting environment for improving quality reliability of a memory device and by minimizing overall loss due to change in a mounting environment thus reducing testing time and cost. The field mounting-type test apparatus includes a mass storage device configured to store logic data simulating a mounting environment of a device under test (DUT) and a tester main frame configured to test the DUT using the logic data.

Field mounting-type test apparatus and method for testing memory component or module in actual PC environment

A method of generating pulses includes setting a cycle based on a frequency of reference clock, determining a total number of the pulses to be generated during the cycle, calculating the number of one or more first reference clocks used to determine a width of one or more first pulses, the number of one or more second reference clocks used to determine a width of one or more second pulses, a first pulse number for the first pulses and a second pulse number for the second pulses on the basis of the cycle and the total number of the pulses, and generating the first pulse number of the first pulse and the second pulse number of the second pulses during the cycle. A motor control system employs the above pulse generating method and a pulse generator using the method to improve accuracy of controllability of a motor by generating the total number of the pulses during a cycle, and decrease a manufacturing cost.

Pulse generating method and pulse generator, and motor control system using the same

An apparatus for eliminating variable offset values of current detecting signals and its method having a current detector for detecting feedback current from a three-phase AC motor and for converting the feedback current into voltage detecting signals containing offset elements, differential amplifiers for differentially operating a feedback analog offset signal and the voltage detecting signals, output amplifiers for amplifying the differentially operated voltage detecting signals to fit within the input range for controlling, an analog/digital converter for converting the amplified signals into digital signals, a control part for adding up the digital signals to a digital offset value and for comparing the digital offset value with a predetermined offset command and for applying a proportional plus integral function to the compared result and for outputting a digital offset signal of a pulse-width modulation waveform, and a digital/analog converter for converting the digital offset signal into the analog offset signal and for providing a feedback loop of the analog offset signal to the differential amplifiers. The disclosed invention can adjust a current detecting signal to a desired level of signal even though the offset element which is contained in the detecting signal of a motor such as a current detecting signal of the ASIPM is being variably changed.

Apparatus and method for eliminating variable offset values of current detecting signals

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Seongnam-si, South Korea

In-su Yang