Skhynix Inc.

In Su Park

Ki Hong Lee

Seung Ho Pyi

Jung Shik Jang

Jung Dal Choi

Mi Seong Park

Dong Sun Sheen

Hye Jeong Cheon

Dong Hun Lee

Jang Won Kim

Do Yeon Kim

Ki Jun Yun

Won Geun Choi

Jae Woong Kim

Jeong Hwan Kim

Woo Pyo Jeong

A semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device including a stacked body including conductive patterns and insulating patterns that are alternately stacked, a filling layer configured to pass through the stacked body, a first channel layer configured to pass through the stacked body and coupled to the filling layer, a second channel layer configured to pass through the stacked body and coupled to the filling layer, a first interposed layer configured to pass through the stacked body and disposed between the first channel layer and the filling layer, a second interposed layer configured to pass through the stacked body and disposed between the second channel layer and the filling layer, and a memory layer surrounding the filling layer, the first and second channel layers, and the first and second interposed layers.

Semiconductor device and method of manufacturing the semiconductor device

A semiconductor device includes a stack structure, a channel layer passing through the stack structure, a memory layer enclosing the channel layer and including first and second openings which expose the channel layer, a well plate coupled to the channel layer through the first opening, and a source plate coupled to the channel layer through the second opening.

Semiconductor device and manufacturing method of a semiconductor device

A semiconductor device includes a gate structure including conductive layers and insulating layers alternately stacked with each other, channel structures passing through the gate structure and arranged in a first direction, a cutting structure extending in the first direction and passing through the channel structures, and a first slit structure passing through the gate structure and extending in a second direction crossing the first direction.

Semiconductor device with improved cell density and manufacturing method of the semiconductor device

A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stacked structure with a cell array region and a contact region with a stepped shape, and a roughness of a first sidewall of the cell array region is greater than that of a second sidewall of the contact region.

Three-dimensional semiconductor memory device

A non-volatile memory device may include a semiconductor substrate, a stack structure and a source structure. The stack structure may be formed on the semiconductor substrate. The source structure may be formed in a slit configured to divide the stack structure. The source structure may include a sealing layer, a source liner, a gap-filling layer and a source contact pattern. The sealing layer may be formed on an inner wall of the slit. The source liner may be formed on a surface of the sealing layer and a bottom surface of the slit. The gap-filling layer may be formed in the slit. The source contact pattern may be formed on the gap-filling layer in the slit. The source contact pattern may be electrically connected with the source liner.

Non-volatile memory device and method of manufacturing the non-volatile memory device

The present discloses provides a memory device and a method of operating the memory device. The memory device includes first main plugs formed in a vertical direction over a substrate and arranged in a first direction, second main plugs, third main plugs arranged between the first and second main plugs, the third main plugs adjacent to the first and second main plugs, and bit lines above the first to third main plugs, wherein each of the first to third main plugs includes first and second sub-plugs facing each other, wherein portions of the first and second sub-plugs included in each of the first and third main plugs are coupled to different select lines, and wherein portions of the first and second sub-plugs included in each of the second and third main plugs are coupled to different select lines.

Memory device storing logical page data and operating method of the memory device

There may be provided a method of manufacturing a semiconductor chip. A layer stack in which first material layers and second material layers are alternately stacked is formed on a semiconductor substrate that includes a chip region and a scribe lane region, and crack propagation guides are formed in a first portion of the layer stack within the scribe lane region.

Methods of manufacturing semiconductor chip including crack propagation guide

A semiconductor device includes a core insulating layer extending in a first direction, an etch stop layer disposed on the core insulating layer, a channel layer extending along a sidewall of the core insulating layer and a sidewall of the etch stop layer, conductive patterns each surrounding the channel layer and stacked to be spaced apart from each other in the first direction, and an impurity region formed in an upper end of the channel layer.

Method for manufacturing a semiconductor device having a channel layer with an impurity region

A method of manufacturing a semiconductor device includes forming a first etch stop pattern on a lower structure including a first region and a second region to expose the second region, stacking a plurality of stack structures on the lower structure to overlap the second region and the first etch stop pattern, forming a stepped stack structure by etching the plurality of stack structures to expose an end portion of the first etch stop pattern, forming a slit passing through the stepped stack structure and the first etch stop pattern, and replacing sacrificial layers of the plurality of stack structures and the first etch stop pattern with conductive patterns through the slit.

Manufacturing method of a semiconductor device

Semiconductor device having a vertical channel layer with an impurity region surrounding a dielectric core

A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.

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Icheon-si, South Korea

In Su Park