Samsung Electronics Co., Ltd.

In-Su Choi

Sun-Young Lim

Young-ho Lee

Seung-Man Shin

Hyun-Sung Shin

Hui-chong Shin

Dimin Niu

Jun-Jin Kong

Hak-soo Yu

Joo-Young Hwang

Sang-Joon Hwang

Hyoung-Joon Kim

Doo-Hwan Oh

Yong-Jun Yu

Jung-Ho Jung

In-Dong Kim

A memory system may comprise a plurality of data strobe transfer paths assigned to a plurality of data transfer paths such that each of the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths. At least one selected data strobe transfer path is selected and data signals transferred through the plurality of data transfer paths are sampled using at least one data strobe signal transferred through the selected data strobe transfer path. Reliability of data communication is enhanced through a redundant data strobe scheme by assigning a plurality of data strobe transfer paths to a plurality of data transfer paths such that the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths.

Interface method of memory system, interface circuitry and memory module

A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.

Memory system for supporting internal DQ termination of data buffer

In a method of operating a memory device, a first write command, a first write address, and first write data are received by a first memory device through a channel. The first write command, received by the first memory device, is sensed by a controller. The controller is connected to the channel and controls a second memory device. The first memory device and the second memory device are different types of memory devices. When the first write command is sensed by the controller, a first write log is generated using the first write address and the first write data. The first write log is stored into a buffer.

Method of operating a memory device

A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.

Semiconductor memory device and computer system including the same

A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.

Device including an external memory connection unit capable of adopting an external memory

A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of a plurality of memory banks of a first memory bank group from among one or more memory bank groups of the memory cell array performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation.

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Hwaseong-si, South Korea

In-Su Choi