Hyundai Electronics Industries Co. Ltd.

Hynix Semiconductor Inc.

In Seok Yeo

Se Aug Jang

Tae Kyun Kim

Tae Ho Cha

Heung Jae Cho

Jong Choul Kim

Kwan Yong Lim

Sahng Kyoo Lee

Dae Gyu Park

Young Bog Kim

Jung Ho Lee

Noh Yeal Kwak

Hyeon Soo Kim

Jin Won Park

Jae Young Kim

Jin Sang Park

Dea Gyu Park

Sang Moo Lee

Seung Chul Lee

Jean Hong Lee

The present invention discloses the single gate CMOS with the surface channel manufactured according to the manufacturing method of the present invention is very advantageous for improving the characteristics, yield and reliability of the device, by performing decoupled plasma nitridation (DPN) process on the gate oxide film of the cell NMOS and the peripheral PMOS, respectively, thereby forming a silicon nitride on the surface of the gate oxide film. Further, the single gate CMOS with the surface channel can be formed more easily through the simplified process in overall, without requiring a separate transient ion implantation process, even when the gate electrode of the n polysilicon layer is used, by having the threshold voltage of the cell NMOS be approximately &plus;0.9V, the threshold voltage of the peripheral PMOS be approximately &minus;0.5V and above, and the threshold voltage of the peripheral NMOS be approximately &plus;0.5V and below. In addition, since the cell NMOS already has &plus;0.9V of threshold voltage, back bias does not have to be applied separately to achieve the &plus;0.9V threshold voltage, and the device with low power consumption is formed successfully.

CMOS of semiconductor device and method for manufacturing the same

There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention forms a Ta film or a TaNx film at a low temperature or forms a first TaNx film in which the composition(x) of nitrogen is 0.45&tilde;0.55, on a gate insulating film in a NMOS region, so that the work function becomes 4.0&tilde;4.4 eV, and also forms a Ta film or a TaNx film at a high temperature or forms a second TaNx film in which the composition(x) of nitrogen is 0.6&tilde;1.4 is formed, on a gate insulating film in a PMOS region, so that the work function becomes 4.8&tilde;5.2 eV. Thus, the present invention can lower the threshold voltage by implementing a surface channel CMOS device both in the NMOS region and the PMOS region.

Method of manufacturing a transistor in a semiconductor device

A method for fabricating a dual metal gate structure for a semiconductor device including deposition of a semiconductor substrate having PMOS and NMOS regions, a first gate having a first insulating layer and a first metal layer is formed in a first region. The first region is either the PMOS or NMOS region, and the remaining region becomes a second region. A dummy gate is formed in the second region. A spacer and a source/drain region are formed for each of the first and dummy gates. The dummy gate, however, is removed to expose a portion of the substrate in the second region. A second gate constructed of a second gate insulating layer and a second metal layer is then formed on the exposed portion of the substrate in the second region.

Method for fabricating a dual metal gate for a semiconductor device

A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (Ti Al ) N film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (Ti Al ) N film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.

Method of manufacturing semiconductor devices with titanium aluminum nitride work function

A method of forming a gate electrode in a semiconductor device which can prevent abnormal oxidation of a titanium silicide layer when performing gate re-oxidation process after a gate electrode having a stacked structure of a doped polysilicon layer and the titanium silicide layer.

Method of forming gate electrode in semiconductor device

A method of forming a semiconductor device gate including the steps of forming a dummy gate insulating layer on a semiconductor substrate having an isolating field oxide layer, successively depositing a dummy gate silicon layer and a hard mask layer on the dummy gate insulating layer, forming a hard mask layer and patterning the dummy gate silicon layer using the mask pattern as an etch barrier, forming a thermal oxide layer at both sidewalls of the dummy gate silicon layer by thermal oxidation on the resultant structure, forming spacers at both sidewalls of the dummy gate silicon layer, depositing an insulating interlayer on the resultant structure, polishing the insulating interlayer to expose the dummy gate silicon layer, forming a damascene structure by removing the dummy gate silicon and insulating layers, depositing a gate insulating layer and a gate metal layer on an entire surface of the semiconductor substrate having the damascene structure, and polishing the gate metal and insulating layers, thereby preventing the undercut at the bottom corners of a damascene groove.

Method for forming a gate in a semiconductor device

The MOSFET fabrication method allows application of a self-aligned contact (SAC) process while maintaining a metal gate, such as a tungsten gate, to have a uniform thickness. The process involves forming a metal oxide film during the formation of a metal gate structure of the MOSFET device. The metal oxide film is formed by subjecting the gate structure through a rapid thermal oxidation (RTO) treatment and then to an N O plasma treatment. The treatments allow the thickness of the metal oxide to be precisely controlled. The metal oxide acts as an insulator, which prevents electrical shorts between the gate structure and a contact plug even if a misalignment of occurs during the SAC process. This is an improvement from the conventional practice of separately forming a SAC barrier film after the formation of the metal gate structure and thus saves money, time, and increases reliability and productivity. Also the performance characteristics of the device is enhanced.

MOSFET device fabrication method capable of allowing application of self-aligned contact process while maintaining metal gate to have uniform thickness

A method for forming an element isolation film of a semiconductor device and the semiconductor device. A pad insulator is constructed on a semiconductor substrate. An over-etching process is performed to recess the semiconductor substrate to a predetermined depth while giving a pad insulator pattern. After an insulator spacer is formed at the side wall of the pad insulator pattern, the exposed region of the semiconductor substrate is thermally oxidized to grow an oxide which is, then, removed to form a recess. An element isolation film is formed in the recess by break-through field oxidation and high temperature field oxidation. The element isolation film thus obtained can prevent the field oxide &ldquo;ungrowth&rdquo; phenomenon and at the same time mitigate the field oxide thinning effect as well as improve the properties of the gate oxide.

Method for forming an isolation region in a semiconductor device and resulting structure using a two step oxidation process

The present invention relates to a method for forming a gate electrode in a semiconductor device that is more tolerant of misalignment during contact formation processing. The improved gate structure reduces the formation of shorts between the gate electrode and subsequently formed conductors such as DRAM bit lines and storage lines. The gate electrode is formed from a damascene metal gate electrode having adjacent insulating spacers by partially etching the metal gate electrode to form a trench; depositing a nitride film; and etching the nitride film to form additional protective insulators above outer portions of the gate electrodes. With these protective insulators in place, subsequent contact processing becomes more tolerant of misalignment, reducing rework and improving yield.

Method for forming gate electrode for a semiconductor device

The present invention provides a method for fabricating an improved gate electrode of a MOSFET device. And the method for fabricating a MOSFET device having a polycide gate to which a titanium silicide is applied comprises the steps of sequentially forming a polysilicon layer on a gate insulating layer and a titanium layer in this order, forming a capping layer on the titanium layer and forming a titanium silicide layer by performing a rapid thermal process in nitrogen atmosphere.

Method for forming polycide gate electrode of metal oxide semiconductor field effect transistor

Disclosed is a method for forming gate electrodes using tungsten formed on a tungsten nitride layer by the chemical vapor deposition(CVD) process rather than the physical vapor deposition(PVD) process. According to the method for forming gate electrodes of the present invention, a silicon layer is formed as a conductive layer for gate electrodes. A tungsten nitride layer is formed on the silicon layer, and then the tungsten nitride layer is thermally treated thereby making a surface of the tungsten nitride layer a first tungsten layer. Next, a second tungsten layer is formed by using the first tungsten layer as a nucleation layer according to the CVD process. According to the present method for forming gate electrodes, tungsten can be deposited by the CVD process rather than by the PVD process. Therefore, those problems such as washing equipment and the particle source which are necessarily accompanied with the PVD process can be prevented, thereby improving productivity and yield.

Method for forming gate electrodes of semiconductor device using a separated WN layer

A method of forming a gate electrode in a semiconductor device which can effectively prevent abnormal oxidation of a metal layer without occurring thermal budget and the deterioration of a gate insulating layer during gate re-oxidation process, is disclosed. In the present invention, one selected from a group consisting of an iridium(Ir) layer, a ruthenium(Ru) layer and an osmium(Os) layer capable of forming a nonvolatile conductive metal oxide layer, is used as a metal layer of a gate electrode instead of a W layer in conventional art. Therefore, although a gate re-oxidation process is performed by a well known method, it is effectively prevented that the metal layer is abnormally oxidized, thereby forming an uniform oxide layer on the side wall of the gate. Furthermore, since the oxide layer is conductive, the resistivity of the gate electrode is reduced.

Method of manufacturing a semiconductor device

SOI device and method for fabricating the same

The present invention relates to a method of manufacturing a junction in a semiconductor device. When forming an elevated source/drain junction (ESD) of a buried channel field effect transistor (BC-FET) using a selective epitaxial growth (SEG) technique, a self-aligned epitaxial silicon (SESS) is formed on the lower portion of a gate side-wall spacer, resulting in the improvement of a short channel characteristic by suppressing a facet occurred when forming an elevated source/drain junction (EDS) of the buried channel field effect transistors (BC-FETs) using a selective epitaxial growth (SEG) technique as well as the increase of the current density by lowering the series resistance of source/drain extension.

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Seoul, South Korea

In Seok Yeo