Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Industry-academic Cooperation Foundation

In-Seok Yeo

Hong-Sik Yoon

Seung-Jae Baik

Zong-liang Huo

Shi-Eun Kim

Seung-hyun Lim

Sun-Woo Lee

Kyong-Hee Joo

Young-Moon Choi

Zong-Liang Huo

Subramanya Mayya Kolake

Ji-Young Kim

Jin-Ho Park

Subramanya Mayya

ZongLiang Huo

Xiaofeng Wang

Kyong-hee Joo

Ki-Hyun Kim

Hyun-Seok Kim

Seung-jun Lee

Sung-Hee Lee

Jae-Hyuk Chang

Kyu-Tae Na

Ki-hyun Hwang

Jun-Kyu Yang

Yong-Won Cha

Sang-ryol Yang

Dae-Hong Ko

Sang-Sig Kim

Kolake Mayya Subramanya

Sang-Yeon Kim

Myung-jong Kim

Mann-Ho Cho

Jeong-Hoon Byeon

Xiao Feng Wang

Xianfeng Wang

Dong-Young Jeong

Hyun-Chul Sohn

A method of forming a metal pattern includes forming a precursor layer including a metal precursor on a substrate, irradiating a light on the precursor layer to form a metal seed layer having a predetermined pattern, and electroless-plating the metal seed layer to form a metal pattern layer.

Method of forming metal pattern and method of manufacturing display substrate having the same

Methods of forming carbon nanotubes include forming a catalytic metal layer on a sidewall of an electrically conductive region, such as a metal or metal nitride pattern. A plurality of carbon nanotubes are grown from the catalytic metal layer. These carbon nanotubes can be grown from a sidewall of the catalytic metal layer. The plurality of carbon nanotubes are then exposed to an organic solvent. This step of exposing the carbon nanotubes to the organic solvent may be preceded by a step of applying centrifugal forces to the plurality of carbon nanotubes. Alternatively, the exposing step may include applying a centrifugal force to the plurality of carbon nanotubes while simultaneously exposing the plurality of carbon nanotubes to an organic solvent.

Methods of forming carbon nanotubes

Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices.

Methods of fabricating semiconductor devices and semiconductor devices fabricated by the same

Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.

Single transistor floating-body DRAM devices having vertical channel transistor structures

A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano line is formed in the nano line arrangement region extending substantially along the length thereof and coupled to the surface of the groove structure to define a nano line structure. Related devices are also discussed.

Nano line structures in microelectronic devices

The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.

Charge trap flash memory device and memory card and system including the same

Provided are a nano filament structure and a method of forming the nano filament structure. The nano filament structure includes a first layer disposed on a substrate, a second layer having a gap of nanometer size disposed on the first layer, a catalyst layer interposed between the first layer and the second layer, and a nano filament. One end of the nano filament is in contact with the catalyst layer and grows by penetrating the gap of the second layer.

Nano filament structure and methods of forming the same

Method of fabricating single transistor floating-body DRAM devices having vertical channel transistor structures

A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected to drains of the transistors, source lines at a second side of the gate electrodes, different from the first side, and connected to sources of the transistors on the semiconductor substrate, and charge storage regions between the gate electrodes and the floating bodies.

Semiconductor memory device having DRAM cell mode and non-volatile memory cell mode and operation method thereof

A memory device includes an insulating layer formed over a substrate, a gate formed over the insulating layer, and charge storage elements disposed over the insulating layer. The charge storage elements are separated from each other and are electrically insulated, and each of the charge storage elements is capable of storing at least one charge. The charge storage elements can include fullerenes.

Semiconductor device and method for forming the same

Provided are a semiconductor device and a method of manufacturing the semiconductor device, for example, a semiconductor device using carbon nanotubes or nanowires as lower electrodes of a capacitor, and a method of manufacturing the semiconductor device. The semiconductor device may include a lower electrode including a plurality of tubes or wires on a semiconductor substrate, a dielectric layer on the surface of the lower electrode, and an upper electrode on the surface of the dielectric layer, wherein the plurality of tubes or wires radiate outwardly from each other centering on the lower portion of the plurality of tubes or wires. Thus, the off current of the capacitor may be increased by increasing the surface area of the lower electrodes of the capacitor.

Semiconductor device and method of manufacturing the same

Methods of forming nano line structures in microelectronic devices

In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

DRAM device and method of manufacturing the same

A semiconductor device includes a substrate, an insulating layer having an opening, the opening exposing a portion of the substrate, a hydrophobic layer covering substantially only a sidewall and a top surface of the insulating layer, and a nanoscale conductive structure on the exposed portion of the substrate.

Semiconductor device having a nanoscale conductive structure

Growing community of inventors

Seoul, South Korea

In-Seok Yeo