Skhynix Inc.

In Seok Kong

Soon Sung An

Jae Hyeong Hong

Min Su Kim

Kwan Su Shon

Yo Han Jeong

Eun Ji Choi

Chan Keun Kwon

Sung Hwa Ok

Jaehyeong Hong

Junseo Jang

Jun Seo Jang

Gwan Woo Kim

Jung Hwan Lee

Dong Seok Kim

Jae Young Park

Sun Ki Cho

Hee Jun Kim

Keun Seon Ahn

Bon Kwang Koo

Dae Ho Yang

Sung Ah Lee

Keun Jin Chang

Dong Wook Jang

Joo Won Oh

Sung Mook Kim

Se Won Kim

Heon Ki Kim

Ki Yong Choi

Beom Kyu Seo

Ji Young Lee

Daeho Yang

Jung Yeop Lee

Se Jin Kang

A voltage generation circuit includes a voltage generation unit configured to generate a reference voltage using a power supply voltage and output the reference voltage through a voltage output node. The voltage generation circuit also includes a pre-charge unit configured to drive the voltage output node using the power supply voltage in response to a pre-charge control signal. The voltage generation circuit further includes a pre-charge control unit configured to generate at least one sampling voltage using the power supply voltage and generate the pre-charge control signal according to a result obtained by comparing the at least one sampling voltage with the reference voltage.

Pre-charge control circuit and voltage generation circuit including the same

A signal transmission circuit comprising: a first data transmission circuit configured to output, through a first data output node thereof and in response to a first operation clock applied to a first clock input node thereof, first output data obtained by sensing and amplifying a first input data pair applied to a first differential input node pair thereof, a clock transmission circuit configured to output through a second data output node thereof, a second operation clock generated in response to the first operation clock applied to a second clock input node thereof while a power supply voltage and a ground voltage are applied to a second differential input node pair thereof, and a first data output circuit configured to output the first output data in synchronization with the second operation clock, wherein the first data transmission circuit is modeled on the clock transmission circuit.

Signal transmission circuit and memory device including the same

A signal input/output circuit includes a signal amplification circuit and a current control circuit. The signal amplification circuit configured to amplify and output an input signal transmitted through an input/output line. The current control circuit configured to induce a reverse virtual current corresponding to an output signal of the signal amplification circuit. The current control unit configured to reflect the reverse virtual current on the input/output line.

Signal input/output circuit and method of operating the signal input/output circuit

A calibration device is coupled to a communication line shared by plural devices. The calibration device is configured to perform an iterative eye width scanning by adjusting a set voltage level by a preset level from a first voltage level to a reference center voltage level, wherein the first voltage level corresponds to a cross point where values of signals or data, which are transmitted via the communication lines, are changed in different directions; and determine, as a zero crossing for the signals or the data, a voltage level corresponding to a largest value among a plurality of eye widths obtained through the iterative eye width scanning.

Calibration device and memory device including the calibration device for a high-speed data I/O operation under a low power condition

A signal generation apparatus includes a glitch rejection circuit including n m-stage inverters coupled in series, and configured to receive an input signal and perform an inverting operation on the input signal, based on a plurality of voltage signals, to generate an output signal and adjust switching threshold voltages of the m-stage inverters, based on the plurality of voltage signals, to generate the glitch-removed output signal, when a glitch occurs in the input signal, a level detection circuit to detect a logic level of the output signal provided from the glitch rejection circuit to generate a level detection signal and a complementary level detection signal, and a voltage signal generation circuit configured to receive the input signal, a complementary input signal, the level detection signal, and the complementary level detection signal to generate the plurality of voltage signals and provide the plurality of voltage signals to the glitch rejection circuit.

Signal generation apparatus capable of rejecting noise

An input buffer circuit includes a signal input circuit and a linear setting circuit. The signal input circuit is configured to receive an input signal to generate an output signal based on a reference voltage and an activation current. The linear setting circuit is configured to compare a voltage of a first modeling node, which may correspond to the input signal, with a voltage of a second modeling node, which may correspond to the reference voltage, to generate a bias voltage for controlling the activation voltage.

Input buffer circuit and semiconductor system including the same

A data transmission circuit may include a plurality of data transmission lines configured to transmit a victim data signal through a victim data transmission line, and transmit an adjacent data signal through an adjacent data transmission line disposed adjacent to the victim data transmission line; and a data input/output circuit configured to control a reference voltage level reflected into the victim data signal on the basis of data pattern information of the adjacent data signal, and compare the victim data signal to the reference voltage level and output the comparison result.

Data transmission circuit and operation method thereof

The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.

Memory device for correcting pulse duty and memory system including the same

Growing community of inventors

Gyeonggi-do, South Korea

In Seok Kong