Samsung Electronics Co., Ltd.

In-Seak Hwang

Yong-Sun Ko

Dae-Hyuk Chung

Ki-Hyun Hwang

Young-wook Park

Won-Jun Lee

Jae-Young Park

Byoung-Moon Yoon

Jung-Hwan Oh

Young-min Kwon

Keum-Joo Lee

Chang-Lyoung Song

Yoo-Sang Hwang

Kyung-Hyun Kim

Kwang-Wook Lee

Han-Joo Lee

Chung-Ki Min

In-joon Yeo

Si-Youn Kim

Ji-Chul Shin

Hoon Jung

Kwang-wook Lee

Yong-sun Ko

Keum-joo Lee

Chang-Iyoung Song

A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.

Etching method for manufacturing semiconductor device

A chemical supply system includes at least two supply pipes for supplying at least two different chemicals; a mixing unit connected to the supply pipes for mixing at least two different chemicals to form a chemical mixture, an exhausting unit for exhausing the chemical mixture externally; and a filtering unit provided between the mixing unit and the exhausting unit for filtering the chemical mixture to prevent chemical particles having more than a predetermined size from being exhausted.

Chemical supply system and chemical mixing apparatus

Cleaning solutions for integrated circuit devices and methods of cleaning integrated circuit devices using the same are disclosed. The cleaning solution includes about 30% aqueous ammonia solution, acetic acid by a volume percent higher then a volume percent of the aqueous ammonia solution, and deionized water by a volume percent higher then the volume percent of the acetic acid. Additionally, disclosed are methods wherein the cleaning solution is formed on integrated circuit substrates having an exposed metal pattern formed thereon, and further providing mega-sonic energy to the film of the cleaning solution.

Cleaning solution including aqueous ammonia solution, acetic acid and deionized water for integrated circuit devices and methods of cleaning integrated circuit devices using the same

Methods of forming an electronic structure can include forming an interlayer insulating layer on a substrate, and forming a storage node comprising a base and sidewalls extending away from the base. The interlayer insulating layer can have a contact hole therein exposing a portion of the substrate. Moreover, the storage node base can be in the contact hole and the sidewalls can extend away from the base and away from the substrate with portions of the sidewalls being within the contact hole and with portions of the sidewalls extending outside the contact hole beyond the interlayer insulating layer away from the substrate. Related structures are also discussed.

Method of forming storage nodes comprising a base in a contact hole and related structures

An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

One-cylinder stack capacitor and method for fabricating the same

In a cleaning solution and a method of cleaning a semiconductor substrate, the cleaning solution includes about 1 to about 10 percent by weight of sulfuric acid, about 0.5 to about 5 percent by weight of aqueous hydrogen peroxide solution, and about 85 to about 98.5 percent by weight of hydrogen fluoric acid solution. Various polymers attached to a metal wiring formed on a substrate are removed by immersing the substrate into the cleaning solution. The substrate is rinsed to remove the cleaning solution remaining on the substrate. Thus, the polymers can be completely removed without damage to the metal wiring and an underlying oxide film.

Cleaning solution and method of cleaning a semiconductor device using the same

A stripping solution is supplied onto the surface of a substrate and an alternating magnetic flux is applied to the substrate. The alternating magnetic flux induces a current in a conductive pattern of the substrate which heats the conductive pattern while the stripping solution is in contact with the substrate. The stripping solution, containing particles to be cleaned off the substrate, is then removed from the substrate.

Method and apparatus for cleaning a semiconductor substrate

A method of forming a self-aligned contact pad for use in a semiconductor device, including: forming a gate having a gate mask formed thereon on a semiconductor substrate, the semiconductor substrate including an active region and a non-active region, forming a spacer on both sidewalls of the gate and the gate mask, forming an interlayer insulating layer over the entire surface of the semiconductor substrate, the interlayer insulating layer including an opening formed on the active region of the semiconductor substrate, forming a conductive material layer over the entire surface of the semiconductor substrate to cover the interlayer insulating layer, etching-back the conductive material layer until the interlayer insulating layer is exposed, and performing a multi-step CMP process to form contact pads in the opening of the interlayer insulating layer, such that the contact pads are electrically insulated from each other.

Method of forming a self-aligned contact pad for use in a semiconductor device

A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 &angst;, preferably 200 &angst; from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.

Shallow trench isolation type semiconductor device and method of forming the same

Cylindrical capacitors and methods of fabricating the same are provided. The cylindrical capacitor includes a cylindrical storage node stacked on a semiconductor substrate. The cylindrical storage node has a base and a stepped sidewall located on the base. The stepped sidewall has at least two sub-sidewalls, which are sequentially stacked, and at least one joint portion that connects a lower sidewall of the sub-sidewalls to an upper sidewall stacked on the lower sidewall. An upper diameter of the respective sub-sidewalls is greater than a lower diameter thereof. Also, the upper diameter of the lower sidewall is greater than the lower diameter of the upper sidewall stacked on the lower sidewall. The method of fabricating the cylindrical storage node having a stepped sidewall includes sequentially forming a plurality of molding layers over a semiconductor substrate. An etch rate of a lower molding layer of the plurality of molding layers being faster than that of an upper molding layer on the lower molding layer with respect to a predetermined etchant. The plurality of molding layers are patterned to form a preliminary storage node hole that exposes a portion of the semiconductor substrate. The patterned molding layers are isotropically etched using the etchant, thereby forming a storage node hole. Therefore, the storage node hole has a stepped sidewall profile. A conformal conductive layer is then formed on the substrate and the conductive layer is planarized until a top surface of the molding layers is exposed.

Cylindrical capacitors having a stepped sidewall and methods for fabricating the same

Methods for manufacturing a semiconductor device, in which a chamfered metal silicide layer is formed by a 2-stage continuous wet etching process using different etchants, thereby resulting in a sufficient insulation margin between a lower conductive layer including the metal silicide layer and the contact plug self-aligned with the lower conductive layer are disclosed. In the manufacture of a semiconductor device, a mask pattern is formed on a metal silicide layer to expose a portion of the metal silicide layer. The exposed portion of the metal silicide layer is isotropically etched in a first etchant to form a metal silicide layer with a shallow groove, and defects due to the silicon remaining on the surface of the metal silicide layer with the shallow groove are removed using a second etchant, to form a metal silicide layer with a smooth surface. Microelectronic structures produced by methods of the present invention are also disclosed.

Growing community of inventors

Suwon, South Korea

In-Seak Hwang