Samsung Electronics Co., Ltd.

In-seak Hwang

Dae-Hyuk Chung

Yong-Sun Ko

Byoung-ho Kwon

Ki-Vin Im

Kwang-Wook Lee

Young-kuk Kim

Bo-un Yoon

Han-jin Lim

Jun-Seok Lee

Moon-han Park

Dong-ho Ahn

Sang-jun Lee

Yoon-Ho Son

Sung-eui Kim

In-Gi Kim

Tai-su Park

Byoung-Yong Gwak

Kyoung-hwan Kim

Keum-joo Lee

Tae-Joon Park

Hye-sung Park

Jong-hyuk Park

Young-sun Koh

Shin Hyoung Kim

Ki-Hyun Hwang

Tae-Won Kim

Seung-Ho Park

Seok-Woo Nam

Suk-Hun Choi

Jae-Jik Baek

Byoung-Moon Yoon

Sang-kyun Kim

Jae-hee Kim

Ki-Jong Park

In-Sang Jeon

Tae-ho Hwang

Keum-Joo Lee

Ho-Kyun An

Mong-sup Lee

Yun-Jeong Kim

Dae-Keun Kang

Jin-Woo Bae

Hao Cui

Soo-Young Tak

Jong-Sun Ahn

Yong-sun Ko

Dae-hyuk Chung

One-Moon Chang

Bo-Wo Choi

Byung-Ho Kwak

Yoon-Kyung Kim

Heon-jae Ha

Byung-Sul Ryu

Young-ho Koh

Hee-sook Cheon

Sang-Hyun Choi

Yang-hee Lee

Jin-Ho Noh

Mong-Sup Lee

Kwang Wook Lee

Bong-Ho Moon

Ju-Yun Cheol

Myung-jae Jang

A semiconductor device including a direct contact and a bit line in a cell array region and a gate electrode structure in a peripheral circuit region, and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate including a cell array region including a first active region and a peripheral circuit region including a second active region, a first insulating layer on the substrate, the first insulating layer including contact holes exposing the first active region, a direct contact in the contact holes, wherein a direct contact is connected to the first active region, a bit line connected to the direct contact in the cell array region and extending in a first direction, and a gate insulating layer and a gate electrode structure, wherein a dummy conductive layer including substantially the same material as the direct contact is in the peripheral circuit region.

Semiconductor device and method of manufacturing the same

In a method of manufacturing a semiconductor device, mask patterns are formed on a semiconductor substrate. An organic layer is formed on the semiconductor substrate to cover the mask patterns. An upper portion of the organic layer is planarized using a polishing composition. The polishing composition includes an oxidizing agent and is devoid of abrasive particles.

Methods of manufacturing semiconductor devices

A method of manufacturing a semiconductor device includes: preparing a wafer in which a first cell area and a second cell area are defined; forming a bottom electrode structure in the first cell area and a dummy structure located in the second cell area; and sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure, wherein the bottom electrode structure includes a plurality of bottom electrodes extending in a first direction in the first cell area and first and second supporters to support the plurality of bottom electrodes, wherein the dummy structure includes a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area, and the second supporter and the second supporter film are at a same level relative to the wafer.

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first bit line structure extending in a first direction, a second bit line structure extending in the first direction and spaced apart from the first bit line structure, a storage contact plug located between the first bit line structure and the second bit line structure, and extending in a second direction perpendicular to the first direction, a first plug insulator located between the first bit line structure and the second bit line structure, and configured to contact a side surface extending in the second direction of the storage contact plug, and a plug isolation pattern located between the first bit line structure and the first plug insulator.

Semiconductor devices having plug insulators

A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.

Methods of fabricating semiconductor devices

A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.

Semiconductor devices having self-aligned contact pads

Methods of manufacturing semiconductor devices having self-aligned contact pads

A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth.

Method of fabricating semiconductor device

A method of manufacturing a semiconductor device includes forming a bit line on a substrate comprising an active region; forming an interlayer insulating layer covering the bit line on the substrate; forming a first hole at a location of the active region through the interlayer insulating layer; forming a dummy contact layer by filling the first hole; forming a mold layer on the interlayer insulating layer and the dummy contact layer; forming a second hole at a location of the dummy contact layer through the mold layer; removing the dummy contact layer in the first hole through the second hole; forming an epitaxial layer on a portion of the active region, which is exposed at a lower surface of the first hole; and forming a lower electrode on internal surfaces of the first hole and the second hole.

Method of manufacturing semiconductor device

In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced.

Memory device

A chemical-mechanical polishing (CMP) apparatus for manufacturing a semiconductor device. The apparatus includes: a spin chuck for supporting and rotating a semiconductor wafer; a polisher comprising a polishing pad for planarizing a surface of the semiconductor wafer, the polisher moving along the surface of the semiconductor wafer by a polishing arm; and a polisher supporting device for supporting the polisher and maintaining the polisher in a horizontal state, while polishing an edge part of the surface of the semiconductor wafer, in order to improve polishing uniformity of a center part and the edge part of the semiconductor wafer. Accordingly, polishing uniformity of the center part and edge part of the semiconductor wafer may be improved, and a height of the polisher supporting device may be optimized according to a polishing degree. Also, the polisher may be easily supported, wear and tear of the support head may be minimized, and the support head may function as a conditioner.

Chemical-mechanical polishing apparatus for manufacturing semiconductor devices

A semiconductor device includes a semiconductor substrate having at least two oblique side surfaces and a first bottom surface in a recessed portion. A gate insulating layer is formed on the recessed portion. A gate electrode is formed on the gate insulating layer. A channel region is formed below the gate electrode. Gate spacers are formed on side surfaces of the gate electrode.

Semiconductor devices including gate structure and method of fabricating the same

In an apparatus and method for removing a photoresist structure from a substrate, a chamber for receiving the substrate includes a showerhead for uniformly distributing a mixture of water vapor and ozone gas onto the substrate. The showerhead includes a first space having walls and configured to receive the water vapor, and a second space connected to the first space so that the water vapor is supplied to and partially condensed into liquid water on one or more walls of the first space. Ozone gas and water vapor without liquid water may be supplied to the second space to form the mixture therein. The showerhead may be heated to vaporize the liquid water on a given surface of the first space.

Apparatus and method for removing a photoresist structure from a substrate

A method of fabricating a semiconductor device includes forming a mask pattern on an active region of a substrate defined by an isolation region. The mask pattern includes an opening therein exposing a portion of the active region. The exposed portion of the active region is etched to define a preliminary gate trench therein including opposing sidewalls and a surface therebetween, where portions of the mask pattern extend to edges of the active region outside the preliminary gate trench. An annealing process is performed on the substrate to form a gate trench from the preliminary gate trench, and gate electrode is formed in the gate trench. The preliminary gate trench and the gate trench have a substantially similar width defined between the edges of the active region including the portions of the mask pattern thereon.

Methods of fabricating recessed channel metal oxide semiconductor (MOS) transistors

A wiring structure of a semiconductor device may have an insulation layer, a spacer and a plug. The insulation layer may be provided on a substrate and may have an opening through which a contact region of the substrate is exposed. The spacer may be provided on a sidewall of the opening. The plug may fill the opening and may include a polysilicon pattern doped with impurities, a metal silicide pattern, and a metal pattern sequentially provided on the substrate.

Wiring structure of a semiconductor device and method of forming the same

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Suwon-si, South Korea

In-seak Hwang