Electronics and Telecommunications Research Institute

In San Jeon

Hyuk Joo Kim

Han Jin Cho

Seong Min Kim

Min-Hyung Cho

Jin Ho Han

Young-deuk Jeon

Young Hwan Bae

Sung Eun Kim

Kyung Soo Kim

Tae Wook Kang

Jae-Jin Lee

Jung Bum Kim

Kwang Il Oh

Young-Su Kwon

Woo Seok Yang

Bon Tae Koo

Kyung Jin Byun

Chan Soo Kim

Mi Young Lee

Ik Soo Eo

Won Jong Kim

June Young Chang

Whan Woo Kim

Ju Yeob Kim

Guee Sang Lee

Disclosed is an encoder including event layer outputs first and second event signals, weight layer applies first and second weights to the first and second event signals respectively, and provides the first event signal in which the first weight is applied and the second event signal in which the second weight is applied to first node, and first spike generation circuit generates first input spike signal of which firing period is changed based on voltage level of the first node. The voltage level of the first node is reduced continuously, increases for first voltage corresponding to the first weight in response to the first event signal activated, and increases for second voltage corresponding to the second weight in response to the second event signal activated.

Encoder and operation method thereof

Disclosed is a neural network accelerator including a maximum value determiner outputting a maximum value based on a first magnitude component corresponding to first input data and a second magnitude component corresponding to second input data, a sign determiner outputting a sign component corresponding to the maximum value among a first sign component corresponding to the first input data and a second sign component corresponding to the second input data, as an output sign component, an offset operator quantizing a difference between the first magnitude component and the second magnitude component and outputting an output offset based on the first sign component, the second sign component, and the quantization result, and a magnitude operator calculating an output magnitude component of an output data based on the maximum value and the output offset. Each of the first input data and the second input data is data on a logarithm domain.

Neural network accelerator configured to perform operation on logarithm domain

Disclosed is a transmitter which includes a channel driver that includes a pull-up transistor and a pull-down transistor connected between a power node and a ground node and outputs a voltage between the pull-up transistor and the pull-down transistor as a transmit signal, and a pre-driver that controls the pull-up transistor and the pull-down transistor in response to a driving signal and controls the channel driver such that the transmit signal is overshot at a rising edge of the driving signal and the transmit signal is undershot at a falling edge of the driving signal.

Transmitter and operating method of transmitter

Disclosed is a receiving circuit, which includes a hysteresis detector that receives an input signal corresponding to a first voltage level and outputs a detection signal having a first threshold voltage and a second threshold voltage, and a level shifter that receives the detection signal, converts the first voltage level of the detection signal to a second voltage level higher than the first voltage level so as to be output as an output signal, and outputs a feedback signal of the second voltage level, and the hysteresis detector receives the feedback signal from the level shifter and adjusts the first threshold voltage and the second threshold voltage based on the feedback signal.

Receiving circuit to process low-voltage signal with hysteresis

Provided is an error correction encoder. The error correction encoder includes input nodes for receiving input words, first encoders for generating first parities by performing a first error correction encoding on each of the input words, an interleaver for generating interleaved words by performing interleaving on the input words, a second encoder for generating a plurality of second parities by performing a second error correction encoding on each of the interleaved words, output nodes for outputting each of the input words, first parity output nodes for outputting the first parities, and second parity output nodes for outputting the second parities.

Error correction encoder, error correction decoder, and optical communication device including the same

A packet combining device for a communication system using hybrid automatic repeat request (HARQ) includes: a HARQ buffer; a combiner configured to combine data which is previously received and stored in the HARQ buffer with newly-received data; and a channel decoder configured to attempt channel decoding by using the combined received data provided from the combiner and provide one or more of log likelihood ratios (LLRs) computed for a systematic bit and a parity bit of the combined received data to the combiner such that the one or more LLRs are combined with the data used for channel decoding.

Packet combining device and method for communication system using hybrid automatic repeat request

An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit.

Parity generating apparatus and map apparatus for turbo decoding

There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.

Distributed video coding apparatus and method capable of controlling encoding rate

Provided are a multiplierless FIR digital filter and a method of designing the same, in which a filtering operation is performed by a small addition/subtraction circuit using extracted information after analyzing the property of a given coefficient and extracting information required for design by only adding/subtracting operations. In the method of designing the multiplierless FIR digital filter, tables are created to extract and store information needed for adding and subtracting operations. An addition table is created to store values obtained by adding the input data synchronized with a clock frequency. Further, a value corresponding to multiplication is obtained by performing extraction and error correction on the added values from the tables, and an adder chain of an output terminal sums up the values and outputs the filtering results, thereby effectively implementing a logic circuit of the multipliedess FIR digital filter.

Multiplierless FIR digital filter and method of designing the same

The present invention relates to a turbo decoder having a state metric, a calculating method using the turbo decoder and a computer-readable recoding medium for executing a calculation method implemented to the turbo decoder. The turbo decoder includes branch metric calculation unit, state metric calculation unit and log likelihood ratio calculation unit. The present invention may reduce calculation steps by simplifying a conventional turbo decode algorithm, reducing a size of a hardware, which the turbo decoder can be implemented in as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The present invention can be implemented in an error correction in wireless communication system and satellite communication system.

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Daejeon, South Korea

In San Jeon