Hynix Semiconductor Inc.

In No Lee

Myung-Kyu Ahn

The present disclosure relates to a method of fabricating a flash memory device. According to the present disclosure, a hard mask layer to which surface roughnesses have been transferred by a metal silicide layer, including the surface roughness, is polished before or during a gate etch process in order to diminish the surface roughnesses. Thus, although surface roughnesses exist in the metal silicide layer, a SAC nitride layer formed over a gate can be prevented from being lost in a subsequent polishing process of a pre-metal dielectric layer, which is performed in order to form a contact plug. Accordingly, a hump phenomenon of a transistor can be improved.

Method of fabricating flash memory device

In a method of fabricating a non-volatile memory device, a semiconductor substrate includes an isolation layer formed in an isolation region, a tunnel insulating layer and a first conductive layer for a floating gate formed in an active region, and a dielectric layer, a second conductive layer for a control gate, and a gate hard mask formed over the first conductive layer including the isolation layer. The second conductive layer is patterned using the gate hard mask as an etch mask. The dielectric layer is patterned so that the first conductive layer, which is exposed as the dielectric layer is etched, is also etched. The first conductive layer is patterned along a pattern of the gate hard mask. Accordingly, at the time of gate patterning, micro bridges between the floating gates can be prevented and a 2-bit failure between neighboring cells is less likely.

Method of fabricating a non-volatile memory device

In a method for manufacturing a nonvolatile memory device, an etch mask layer formed on a dielectric layer to define contact holes in the dielectric layer is slope-etched to form an etch mask pattern having an opening wider at the upper end thereof than the lower end thereof. Thus, the contact holes are defined in the dielectric layer to have a finer size than the upper end of the opening of the etch mask pattern. The method for manufacturing a nonvolatile memory device includes forming an etch mask pattern on a dielectric layer such that a width of a lower end of each opening defined in the etch mask pattern is less than a width of an upper end thereof; and defining contact holes by removing portions of the dielectric layer using the etch mask pattern.

Method for manufacturing a nonvolatile memory device

A method of forming a gate pattern of a flash memory device may include forming a tunnel dielectric layer, a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, a metal electrode layer, and a hard mask film over a semiconductor substrate. The metal electrode layer may be etched such that a positive slope of an upper sidewall may be formed larger than a positive slope of a lower sidewall of the metal electrode layer. The conductive layer for the control gate, the dielectric layer, and the conductive layer for the floating gate may then be etched. High molecular weight argon gas, for example, may be used to improve an anisotropic etch characteristic of plasma. Over etch of a metal electrode layer may be decreased to reduce a bowing profile. Resistance of word lines can be decreased and electrical properties can be improved.

Method of forming gate pattern of flash memory device including over etch with argon

Disclosed herein is a method of manufacturing semiconductor devices. After first isolation trenches are formed in a cell region, second isolation trenches are formed in a peripheral region by an etch process using a photoresist as a mask. As such, top corner portions of an active substrate of the peripheral region are rounded. It is thus possible to fundamentally prevent a hump phenomenon incurred by thinning of the gate oxide film.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes providing a semiconductor substrate in which a floating gate pattern is formed. A dielectric layer, a conductive layer for a control gate, a tungsten silicide layer, a first silicon oxynitride layer, a hard mask layer, a second silicon oxynitride layer and an Organic Bottom Anti-Reflective Coating (BARC) layer are formed over the semiconductor substrate including the floating gate pattern. The BARC layer, the second silicon oxynitride layer, the hard mask layer and the first silicon oxynitride layer are removed. The tungsten silicide layer and the conductive layer for the control gate are removed. The dielectric layer is removed to form spacers on sides of the floating gate. The floating gate is then removed.

Method of manufacturing a semiconductor device

A method of manufacturing a flash memory device. An etch process for controlling the effective field height of isolation layers is performed using a dry etch process on condition that an excessive amount of polymer is generated, thus forming first spacers on sidewalls of a floating gate pattern. The first spacers serve as an etch barrier layer when the isolation layers of regions exposed when a control gate and a floating gate are formed subsequently are etched, so that a second spacer is formed on sidewalls of the semiconductor substrate of an active region. Accordingly, exposure and damage of the sidewalls of the semiconductor substrate can be prevented and the reliability of devices can be improved.

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Icheon-si, South Korea

In No Lee