Vitelic Corporation

Other

In-Nan Wu

James T Koo

Jun Y Kim

King C Wang

Francis C Hung

Jon C Zierk

Kong-Yeu Han

The present invention provides an extended memory capability without requiring a much faster cache memory. This is done by providing address latches on the same chip as the cache memory and providing the most significant address bit from the address latches to be combined with the output of appropriate interface logic. The result of this combination is provided as address control signal along a path to the memory which does not require as long an access time as the rest of the addresses.

Expanded cache memory system

An output buffer circuit is provided for use with a first external voltage which provides voltage at a first level, the output buffer circuit comprising: an output terminal; a second voltage supply for providing voltage at a second level less than the first level; an n-channel pull-up transistor including a drain coupled to the first voltage supply and including a source coupled to the output terminal; a p-channel pull-up transistor including a drain coupled to the output terminal and a source coupled to the second voltage supply; an n-channel pull-down transistor including a drain coupled to the output terminal; a bootstrapping turn-on circuit for raising a gate of the n-channel pull-up transistor to a raised voltage level which is above the first voltage level such that the n-channel pull-up transistor becomes turned on; a turn-off circuit for turning off the n-channel pull-up transistor when the output terminal has been substantially pulled up to the second voltage level; and a turn-on circuit for turning on the p-channel pull-up transistor when the output voltage at the output terminal has been substantially pulled up to the second level.

Pulsed bootstrapping output buffer and associated method

The present invention is a controller for producing a dual port function from a single port memory with an improved memory cycle time. An address or control signal transition for one port generates an access request signal for that port. The access request signal both (1) blocks an access request by the other port for its duration and (2) generates a series of signals for a memory access for the selected port. A multiplexer for providing addresses to the memory core from two ports is switched to select a second port while a first port access is in progress. The output of the multiplexer is not enabled until the memory core access is completed. Thus, the set-up time for the second set of addresses is allowed to overlap the memory core access time for the first set of addresses thereby reducing overall cycle time.

Controller for dual ported memory

Growing community of inventors

Sunnyvale, CA, United States of America

In-Nan Wu