Skhynix Inc.

Mimirip LLC

In Jong Jang

Kyu Min Lee

The present disclosure relates to an operation method of a storage device, which is for overcoming the instability of the storage device caused by throttling cancellation. An operation method of a memory controller may include: acquiring a temperature of a memory; determining, on the basis of the temperature of the memory, to start a throttling operation that reduces performance of the memory; determining whether the throttling operation is cancelled; and recovering the throttling operation, which alleviates instability of the memory caused by the throttling cancellation.

Storage device and throttling operation method thereof

Embodiments of the present disclosure relate to a controller and operation method thereof. According to embodiments of the present disclosure, the controller may include i) a plurality of sub-circuits and ii) a processor configured to: determine the state of the plurality of sub-circuits, determine whether activation conditions corresponding to the plurality of sub-circuits are satisfied at a first time point, and control the controller to operate in an activation mode or in a low-power mode at a second time point, depending on whether the activation conditions corresponding to the plurality of sub-circuits are satisfied.

Controller executing activation mode or low power mode based on state of multiple sub-circuits and operating method thereof

A storage device may enter a plurality of intermediate power states sequentially while entering from a first power state to a second power state. The storage device may check background flag information while entering each of the plurality of intermediate power states, and execute a target background operation, executable in a first intermediate power state, based on the background flag information.

Storage device for executing background operation based on power state and operating method thereof

A memory system includes: a plurality of memory dies each including a plurality of memory blocks each including a plurality of pages, each of the memory dies being configured to store therein map data having a tree structure and a memory controller configured to organize super blocks each including memory blocks from the respective memory dies, configured to control an operation of copying data from a first memory block to a second memory block among the plurality of memory blocks and configured to update the map data according to the operation.

Memory controller for controlling memory dies and memory system including the memory controller

A storage device may comprise a memory including a plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a controller. The controller may assess an external environmental state when a read operation on the memory fails and control a read retry operation using at least one of at least two read retry tables that are set for each of at least two attributes of a first sampling factor and each of at least two attributes of a second sampling factor according to the external environmental stat.

Memory for improving performance of read retry operation, storage device, and method for operating storage device

A memory system includes: a storage device for storing data; a system memory in which normal firmware and debugging firmware are stored; a firmware implementer for implementing the normal firmware or the debugging firmware; and a controller for controlling the storage device in a normal mode in which the memory system is driven by the normal firmware. When an error detected in the normal mode is uncorrectable, the controller uploads the debugging firmware stored in the system memory to the firmware implementer to change the normal mode to a debugging mode. The firmware implementer performs a debugging operation on the storage device by implementing the uploaded debugging firmware.

Memory system and operation method of the memory system

The present disclosure relates to a memory controller which supports an interworking method for a test between an external device and a storage device, and a host. The memory controller proposed in the present disclosure may include a first interface configured to communicate with an external device, a second interface configured to communicate with a memory, a command queue configured to store commands received from the external device and a processor configured to perform a control operation according to a command stored in the command queue, and suspend the performance of the control operation according to the command for a waiting time corresponding to a value of a mutex counter for the command, when a mutex flag for the command is activated.

Interworking method external device and storage device

Provided is an operation method of a memory controller which includes obtaining first read data from a second external device based on a first read command received from a first external device and performing error correction and decoding on the first read data to determine whether reading is successful or unsuccessful, performing a hard decoding-based read recovery operation and a soft decoding-based read recovery operation when a read failure occurs as a result of the first read operation, determining whether there is a second read command queued when the hard decoding-based read recovery has failed, temporarily stopping the read recovery operation for the first read data when there is the second read command queued and obtaining second read data by reading data from the second external device based on the second read command and performing error correction and decoding on the second read data.

Storage device and read recovery method thereof

Provided herein may be an electronic device and a method of operating the same. The electronic device may include a memory device including a replay protected memory block (RPMB) configured to store security data, a memory controller configured to control the memory device, and a host device configured to verify, using a password, an external device coupled thereto wherein the memory controller controls the memory device to read, when the external device is verified, the security data, and wherein the host device is further configured to encrypt the read security data, and transmit, to the verified external device, the encrypted security data, a decryption key for decrypting the encrypted security data, and an RPMB key for accessing the security data.

Electronic device and method of operating the same

A memory system includes a non-volatile memory device and a controller. The non-volatile memory device includes a first memory region and a second memory region. The controller stores, into the second memory region, copied data of original data stored in the first memory region and an address of the first memory region while storing, into the first memory region, an address of the second memory region, when detecting occurrence of a critical event.

Memory system and operating method thereof

Memory systems and operating methods of the memory systems are disclosed. In an implementation, a memory system includes a system buffer including buffer areas to which addresses are allocated, and configured to store data in the buffer areas, and a buffer manager configured to designate an address of a buffer area in which a defect occurs as a defect address by comparing a first parity bit for data stored in the system buffer with a second parity bit that is obtained by a computation based on the data stored in the system buffer, and block access to the buffer area designated as the defect address.

Memory system having system buffer and method of storing data by using the system buffer

A data processing system includes a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.

Apparatus and method for correcting an error in data transmission of a data processing system

A memory system may include: a memory device including a plurality of memory cells, and a controller including: an internal reception queue suitable for queueing a command queued in an external transmission queue, the command being externally provided to the controller, and an internal transmission queue suitable for queueing a response to the command, the response being transmitted from the controller and to be queued in an external reception queue, wherein the controller is suitable for controlling the memory device on the basis of the command to generate the response.

Memory system in which a host and a controller store a command and a response to the command by using a circular queue

A computing system includes host and a storge device. The host includes a host memory and a user interface. The storage device provides the host with a first request including device setting inquiry information, and sets a device configuration based on a first response to the device setting inquiry information received from the host. The host provides the storage device with the first response acquired from a user through the user interface in response to the first request. The device setting inquiry information includes at least one of information on allocation of a map buffer in the host memory, information on allocation of a write buffer in a buffer region of the storage device, or information on a power level of the storage device.

Computing system of setting device configuration and operating method thereof

Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, when updating a target firmware, a memory system may receive, from a host, a temporary firmware for increasing the size of a buffer from a preset first size to a second size equal to or greater than the size of the target firmware, may load and execute the temporary firmware into a processor, may receive the target firmware from the host and write the target firmware to the buffer, and may write the target firmware to the memory device.

Growing community of inventors

Icheon-si, South Korea

In Jong Jang