Skhynix Inc.

Korea University Research and Business Foundation

Postech Academy-industry Foundation

In Hwa Jung

Yong Ju Kim

Chul Woo Kim

Dong Yoon Kim

Jae Yoon Sim

Min Seob Lee

A data input/output device includes a control circuit configured to generate a plurality input control signals in synchronization with a write clock, to perform a domain crossing operation of converting a write clock into a read clock, and to generate a plurality of output control signals based on an output counting signal generated through the domain crossing operation, and a data input/output circuit configured to latch a plurality of pieces of internal data input in parallel in synchronization with the plurality of input control signals, and to serialize the latched plurality pieces of internal data to generate data in synchronization with the plurality of output control signals.

Data input/output device for performing data input/output operation using pipe circuit

A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers, and provides the second timing information corresponding to the timing differences to the transceivers.

Test apparatus

A frequency divider may be provided. The frequency divider may be configured to generate a division signal having a variable cycle according to transition timing information and a division ratio signal.

Frequency divider regarding variable division ratio

An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.

All digital phase locked loop

A duty correction circuit may be provided. The duty correction circuit may include a control circuit configured to generate a duty correction control signal by detecting edges of first and second differential clock signals. The duty a duty correction clock signal generation circuit may be configured to generate a duty correction clock signal according to edges of the duty correction control signal.

Duty correction circuit

A phase and frequency control circuit may be provided. The phase and frequency control circuit may include a division circuit configured to generate a plurality of divided signals by dividing an input signal. The phase and frequency control circuit may include a timing control circuit configured to generate a plurality of timing control signals by sampling the plurality of divided signals according to a phase control code and a sampling reference signal.

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Hwaseong, South Korea

In Hwa Jung