Samsung Electronics Co., Ltd.

In Huh

Changwook Jeong

Chang-wook Jeong

Jeong-hoon Ko

Kwang-il Park

Seung-ju Kim

Hyojin Choi

Tae-ho Lee

Youn-sik Park

Hyo-jin Choi

Min-Chul Park

Sanghoon Myung

Joon-wan Chai

Younsik Park

Hyeon Kyun Noh

Hyunjae Jang

Young-min Oh

Jun-haeng Lee

Hyun-sun Park

Seungju Kim

Jae-jun Lee

Tae Ho Lee

Jun Haeng Lee

Chang Wook Jeong

Yongwoo Lee

Youngmin Oh

Seong-Je Kim

Jeonghoon Ko

Hyun Sun Park

Jaecheol Lee

Min Chul Park

Chan Young Hwang

Younggu Kim

Jaemyung Choe

Joonwan Chai

A method of clustering patterns of an integrated circuit includes; providing a pattern image and numeric data, as input data corresponding to a first pattern to a first model, wherein the first model is trained by a plurality of sample images and a plurality of sample values, obtaining a content latent variable using the first model, and grouping a plurality of content latent variables corresponding to a plurality of patterns into a plurality of clusters based on a Euclidean distance, wherein the numeric data represents at least one attribute of the first pattern.

Method and system performing pattern clustering

A system verification method includes generating a first verification vector as a result of a first action of an agent, the first verification vector referring to an observation corresponding to at least one state already covered, from among states of elements of a target system, identifying a first coverage corresponding to at least one state covered by the first verification vector, from among the states of the elements, updating the observation by reflecting the first coverage in the observation, and generating a second verification vector through a second action of the agent, the second verification vector referring to the updated observation.

Method and apparatus with system verification based on reinforcement learning

Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

Simulation system for semiconductor process and simulation method thereof

A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Device for generating verification vector for circuit design verification, circuit design system, and reinforcement learning method of the device and the circuit design system

A method of selecting a model of machine learning executed by a processor is provided. The method includes: receiving at least one data-set; configuring a configuration space for machine learning of the at least one data-set; extracting, from the at least one data-set, a meta-feature including quantitative information about the data-set; calculating performance of the machine learning for the at least one data-set based on a plurality of configurations included in the configuration space; executing meta-learning based on the meta-feature, the plurality of configurations, and the calculated performance; and optimizing the configuration space based on a result of executing the meta-learning.

Method and apparatus for selecting model of machine learning based on meta-learning

An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.

Electronic devices generating verification vector for verifying semiconductor circuit and methods of operating the same

A method for detecting defects in a semiconductor device includes pre-training a pre-trained convolutional neural network (CNN) model using a sampled clean data set extracted from a first data set; training a normal convolutional neural network model and a label-noise convolutional neural network model using first data of the first data set and the pre-trained convolutional neural network model. The method also includes outputting a first prediction result on whether second data of a second data set is good or bad using the second data and the normal convolutional neural network model; and outputting a second prediction result on whether second data is good or bad using the second data and the label-noise convolutional neural network model. The first prediction result is compared with the second prediction result to perform noise correction when there is a label difference. Third data created as results of the noise correction is added to the sampled clean data set. The normal convolutional neural network model and the label-noise convolutional neural network model are additionally using the sampled clean data set with the third data added.

Method for detecting defects in semiconductor device

A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

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Seoul, South Korea

In Huh