Samsung Electronics Co., Ltd.

In-Gyu Park

Chan-Ho Lee

Jong-Hoon Jung

Dong-Wook Seo

Tae-Joong Song

Hyun-Min Choi

Gyu-Hong Kim

Jae-Seung Choi

Hyun-Su Choi

Soung-Hoon Sim

Jung-Hak Song

A scan chain circuit includes first through N-th flip-flops connected in series to sequentially transfer data in response to a control signal, where N is an integer greater than 1. In the first through N-th flip-flops, the data are transferred in a first direction from the first flip-flop to the N-th flip-flop. The control signal is applied to the first through N-th flip-flops in a second direction opposite to the first direction from the N-th flip-flop to the first flip-flop.

Scan chain circuit and integrated circuit including the same

An e-fuse test device is provided. The e-fuse test device may include a first transistor, and a fuse array connected to a source/drain terminal of the first transistor. The fuse array may include n fuse groups, each of the fuse groups may include one end, the other end, and m first fuse elements connected in series to each other between the one end and the other end, the one end of each of the fuse groups may be connected to each other, and the other end of each of the fuse groups may be connected to the source/drain terminal of the first transistor, and the n and m are natural numbers that are equal to or larger than two.

E-fuse test device and semiconductor device including the same

A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.

Negative voltage generator and semiconductor memory device

A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three power gating transistors are sequentially turned ON. The second and third power gating transistors turn ON sequentially in response to the increasing voltage level of the bus. The timing points when the second and third power gating transistors are sequentially turned ON is based upon detecting the gradually increasing the voltage level of the internal power supply voltage. The size of the first power gating transistor may be smaller than the size of the second power gating transistor, and the size of the second power gating transistor may be smaller than the size of the third power gating transistor.

Power gating circuit, system on chip circuit including the same and power gating method

Each memory block of a memory device a plurality of memory cells connected to a plurality of bit line pairs, a column selecting circuit, and a pre-charge and write control circuit. The column selecting circuit includes a plurality of CMOS transmission gates, each CMOS transmission gate including an NMOS transistor connected between one bit line of a bit line pair and a sense bit line of a sense bit line pair, and a PMOS transistor connected between the one bit line and one of the write bit lines of a write bit line pair. During a write operation, only the NMOS transistor of a selected one of the CMOS transmission gates is turned on, and the PMOS transistor of the selected CMOS transmission gate and the PMOS and NMOS transistors of all of the CMOS transmission gates except the selected one are all turned off.

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Seoul, South Korea

In-Gyu Park