Samsung Electronics Co., Ltd.

In Gyu Baek

Tae Yon Lee

Doo Won Kwon

Jin Yong Choi

Gwi-Deok Ryan Lee

Seung H Yoo

Kwan Sik Kim

Hong Sun Hwang

Joo Sung Moon

Sung Hyun Yoon

Myung Won Lee

Tae Young Song

Hae Min Lim

Min Jung Chung

Chul Woo Park

Kwang-Min Lee

Dong Hyun Sohn

Min-Jun Choi

Sang Hoon Uhm

Kyoung Won Na

Hak Soo Yu

Jae Sung Hur

Mu Jin Seo

Su A Kim

Seok Jin Kwon

Bom I Sim

An image sensor includes: a substrate including a first surface and a second surface on which light is incident, the second surface being opposite to the first surface; a photoelectric converter provided in the substrate; a first metal layer provided on the first surface of the substrate; a second metal layer provided on the first metal layer; and a capacitor layer provided between the first metal layer and the second metal layer, wherein the capacitor layer includes: a first lower electrode electrically connected to the first metal layer, a first upper electrode electrically connected to the second metal layer, a second upper electrode spaced apart from the first upper electrode and electrically connected to the second metal layer, a first capacitor provided between the first lower electrode and the first upper electrode, and a second capacitor provided between the first lower electrode and the second upper electrode.

Image sensor

Image sensors are provided. The image sensor may include a substrate including a first surface and a second surface opposite the first surface, a photoelectric conversion layer in the substrate, and a lower capacitor connection pattern on the first surface of the substrate. The second surface of the substrate may be configured to receive incident light. The lower capacitor connection pattern may include a capacitor region and a landing region protruding from the capacitor region. The image sensors may also include a capacitor structure including a first conductive pattern, a dielectric pattern, and a second conductive pattern sequentially stacked on the capacitor region, a first wire on the capacitor structure and connected to the second conductive pattern, and a second wire connected to the landing region. The first conductive pattern may be connected to the lower capacitor connection pattern. A surface of the first wire facing the substrate and a surface of the second wire facing the substrate may be coplanar.

Image sensors

A method of manufacturing an image sensing apparatus includes: forming a first substrate structure including a first region of a pixel region, the first substrate structure having a first surface and a second surface; forming a second substrate structure including a circuit region for driving the pixel region, the second substrate structure having a third surface and a fourth surface; bonding the first substrate structure to the second substrate structure, such that the first surface is connected to the third surface; forming a second region of the pixel region on the second surface; forming a first connection via, the first connection via extending from the second surface to pass through the first substrate structure; mounting semiconductor chips on the fourth surface, using a conductive bump; and separating a stack structure of the first substrate structure, the second substrate structure, and the semiconductor chips into unit image sensing apparatuses.

Image sensing apparatus

An image sensor includes a substrate, first and second insulating structures, a first wiring structure, a through via, and first and second connection patterns. The substrate includes a sensor array region and a pad region. The first insulating structure is disposed on a second surface of the substrate. The first wiring structure is formed in the first insulating structure and includes first conductive layers and first vias. The through via passes through the substrate in the pad region and connects to the first wiring structure. The first connection pattern is connected to the first wiring structure. The second insulating structure is disposed on a fourth surface of the first insulating structure. The second connection pattern is connected to the first connection pattern. The first conductive layers include a first wiring, and a second wiring spaced farther from the substrate than the first wiring. The through via contacts the second wiring.

Image sensor and method of fabricating the same

An image sensor includes a semiconductor substrate providing a plurality of pixel regions, a semiconductor photoelectric device disposed in each of the plurality of pixel regions, an organic photoelectric device disposed above the semiconductor photoelectric device, and a pixel circuit disposed below the semiconductor photoelectric device. The pixel circuit includes a plurality of driving transistors configured to generate a pixel voltage signal from an electric charge generated in the semiconductor photoelectric device and the organic photoelectric device. A driving gate electrode of at least one of the plurality of driving transistors has a region embedded in the semiconductor substrate.

Image sensor and an image processing device including the same

Image sensing apparatus and manufacturing method thereof

An image sensor configured to provide improved reliability may include a charge passivation layer that includes a multiple different elements, each element of the different elements being a metal element or a metalloid element. The different elements may include a first element of a first group of periodic table elements and a second element of a second, different group of periodic table elements. The charge passivation layer may include an amorphous crystal structure.

Image sensors and methods of fabricating the same

A resistive memory device and method of initialization are provided. The resistive memory device includes a first group of resistive memory cells connected between bit lines and a first plate and a second group connected between bit lines and a second plate. First and second initialization voltages are respectively applied to the first and second plates outside a normal path associated with a normal operation of the resistive memory cells.

Resistive memory devices, initialization methods, and electronic devices incorporating same

Provided is a semiconductor resistive memory device. The resistive memory device includes a plurality of unit cells. A source line and a data input/output line of the unit cells may be selectively connected to have a substantially same voltage level for equalization when the unit cells are in inactive or unselected state. The equalization may decrease current consumption and protect write error, and protect leakage current.

Resistive memory device having voltage level equalizer

Growing community of inventors

Seoul, South Korea

In Gyu Baek