Samsung Electronics Co., Ltd.

Seoul National University

Postech Academy-industry Foundation

In-gyu Baek

Jang-Eun Lee

Moon-Sook Lee

Jin-Shi Zhao

Eun-Kyung Yim

Se-Chung Oh

Hong-Sun Hwang

Hyun-Jun Sim

Dong-Chul Kim

Chul-woo Park

Hyun-Jo Kim

Hak-soo Yu

Jun-Soo Bae

Masayuki Terai

Young-Ki Ha

Man Chang

Kyung-Tae Nam

Jun-Ho Jeong

Lijie Zhang

Yeong-taek Lee

Sang-jin Park

Dae-seok Byeon

Myoung-jae Lee

Min-Young Park

Seung-eon Ahn

Yong-Kyu Lee

Hong-Sik Yoon

Kyung-tae Nam

Gang Zhang

Young-Kwan Cha

Chan-Jin Park

Hyung-yong Kim

Kyung-rae Byun

Shi Li Quan

Jin-yong Choi

Dong-Hyun Sohn

Seug-gab Park

Sun-ae Seo

Byeong-Chan Lee

Byung-Gook Park

Hyung-Rok Oh

Sang-Bom Kang

Young-Bae Kim

In-Sun Park

Yong-Ho Ha

Hyun-Kook Park

Kwan-Young Oh

In-Kyeong Yoo

Kyung-Chang Ryoo

Sun-Ae Seo

Hyeong-jun Kim

Youn-Seon Kang

Kyung-seok Oh

Young-Kug Moon

Jin-hyoung Kwon

Hyun-Su Ju

Woo-bin Song

Han-Sin Lee

Dong Chul Kim

Hyun-sang Hwang

Jinshi Zhao

Byoung-ho Park

Heung-Kyu Park

Seong-Ho Song

Jeong-hoon Oh

Myung-jong Kim

Xiang-Shu Li

Sang-heon Lee

Hyun-Jun Shim

The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.

Three-dimensional image sensor based on structured light

A method for operating a memory device includes sensing a change in temperature of the memory device, adjusting a level of a reference current for a read operation, and reading data from memory cells of the memory device based on the adjusted level of the reference current. The level of the reference current is adjusted from a reference value to a first value when the temperature of the memory device increases and is adjusted from the reference value to a second value when the temperature of the memory device decreases. A difference between the reference value and the first value is different from a difference the reference value and the second value.

Resistive memory device with temperature compensation, resistive memory system, and operating method thereof

A method of controlling a resistive memory device includes: accessing a first pulse power specification satisfying a memory cell coefficient associated with at least a first of a plurality of memory cells included in a memory cell array; generating a first pulse power according to the accessed first pulse power specification; and performing a write operation on at least the first of the plurality of memory cells using the generated first pulse power.

Resistive memory devices and methods of controlling resistive memory devices according to selected pulse power specifications

A method for operating a memory device includes sensing a temperature of the resistive memory device, setting a level of a set voltage or current for writing to a memory cell based on the temperature, setting a level of a reset voltage for reset writing to the memory cell based on the temperature, and performing a write operation on the memory cell based on the level of the set voltage or current and the level of the reset voltage. The memory device may be a resistive memory device.

Resistive memory device, resistive memory system, and operating method thereof

A resistive memory device includes a switching device disposed on a lower interconnection, a resistor element disposed on the switching device, and an upper interconnection disposed on the resistor element. The switching device includes a diode electrode, a high-concentration lower anode disposed on the diode electrode, a middle-concentration lower anode disposed on the lower high-concentration anode electrode, a common cathode disposed on the middle-concentration lower anode, a low-concentration upper anode disposed on the common cathode, and an high-concentration upper anode disposed on the low-concentration upper anode. The peak dopant concentration of the middle-concentration lower anode is at least 10 times greater than the peak dopant concentration of the low-concentration upper anode.

Resistive memory device having asymmetric diode structure

A semiconductor memory device includes pillars extending upright on a substrate in a direction perpendicular to the substrate, a stack disposed on the substrate and constituted by a first interlayer insulating layer, a first conductive layer, a second interlayer insulating layer, and a second conductive layer, a variable resistance layer interposed between the pillars and the first conductive layer, and an insulating layer interposed between the first pillars and the second conductive layer.

Semiconductor memory device having three-dimensional cross point array

Provided is a method of fabricating a memory device. The method includes defining a cell region and a driving region on a substrate, forming driving transistors on the driving region, forming a first bit line in the cell region, a first unit memory cell disposed on an upper surface of the first bit line, a word line disposed on upper surfaces of the first unit memory cells, and a second unit memory cell disposed on an upper surface of the word line, forming a planarization layer configured to fill between the second unit memory cells, and including second bit line grooves on the upper surfaces of the first bit lines, bit line contact vias in the second bit line grooves, floating electrode grooves on upper surfaces of ends of the word lines, and a first floating contact via and a second floating contact via in each of the floating electrode grooves, simultaneously forming second bit lines in the second bit line grooves, bit line contact electrodes in the bit line contact vias, floating electrodes in the floating electrode grooves, first floating contact electrodes in the first floating contact vias, and second floating contact electrodes in the second floating contact vias.

Methods of fabricating memory devices

A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen.

Nonvolatile memory devices and methods of forming the same

A method of fabricating a memory device includes defining a cell region on a substrate and defining a dummy region around the cell region, forming bit lines on a top surface of the substrate, the bit lines extending in one direction, forming cell vertical structures on top surfaces of the bit lines corresponding to the cell region, each cell vertical structure including a cell diode and a variable resistive element, forming dummy vertical structures on top surfaces of the bit lines corresponding to the dummy region, each dummy vertical structure including a dummy diode and a variable resistive element, and forming word lines in contact with top surfaces of the cell vertical structures and dummy vertical structures, the word lines intersecting the bit lines at right angles. The cell diode includes a first impurity pattern and a second impurity pattern, the dummy diode includes a first lightly doped impurity pattern and a second impurity pattern, and the variable resistive element includes a first electrode, a variable resistor, and a second electrode.

Method of fabricating a variable reistance memory device

A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

Resistive memory cells and devices having asymmetrical contacts

A semiconductor device includes a first horizontal molding pattern, a horizontal electrode pattern disposed on the first horizontal molding pattern, and a second horizontal molding pattern disposed on the horizontal electrode pattern. A vertical structure extends through the horizontal patterns. The vertical structure includes a vertical electrode pattern, a data storage pattern interposed between the vertical electrode pattern and the horizontal patterns, a first buffer pattern interposed between the data storage pattern and the first molding pattern, and a second buffer pattern interposed between the data storage pattern and the second molding pattern and spaced apart from the first buffer pattern.

Semiconductor devices with vertical structure including data storage layer or pattern

Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same

A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.

Nonvolatile memory devices that use resistance materials and internal electrodes

A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.

Non-volatile memory devices having resistance changeable elements and related systems and methods

Growing community of inventors

Seoul, South Korea

In-gyu Baek