Samsung Electronics Co., Ltd.

In-Dal Song

Jung-Hwan Choi

Yong Bo Shim

Jeong-Kyoum Kim

Seong-Jin Jang

Young Jae Choi

Kyung-Soo Ha

Hun-Dae Choi

Seok-Hun Hyun

Seong-Hwan Jeon

Hye-Seung Yu

Won-Joo Yun

Hyunui Lee

Jin-Seok Heo

Kyoung-Tae Kang

Tae-Sik Na

A data alignment circuit of a semiconductor memory device including: a data sampling circuit configured to receive a data sequence and an internal data strobe signal, wherein the data sampling circuit samples the data sequence based on the internal data strobe signal to generate first and second data sequences; a division circuit configured to receive a clock signal and the internal data strobe signal, divide the clock signal to produce a divided clock signal and output an alignment control signal by sampling the divided clock signal based on the internal data strobe signal; and a data alignment block configured to receive the first and second data sequences, and the alignment control signal, and align the first and second data sequences in parallel to output internal data.

Data alignment circuit of a semiconductor memory device, a semiconductor memory device and a method of aligning data in a semiconductor memory device

Provided is a memory device configured to perform a calibration operation without having a ZQ pin. The memory device includes a calibration circuit configured to generate a pull-up calibration code and a pull-down calibration code which termination of a data input/output pad for impedance matching in the data input/output pad is controlled. The calibration circuit performs a first calibration operation for trimming first and second reference resistors based on an external resistor to be connected to a pad, and a second calibration operation for generating the pull-up calibration code and the pull-down calibration code based on the trimmed second reference resistor.

Memory device for performing calibration operation

A memory module includes memory devices arranged in ranks and columns and designated in first and second groupings, the first grouping includes memory devices arranged in only a first rank nearest a memory controller and directly connected to the memory controller, the memory devices in the second grouping are indirectly connected to the memory controller via a corresponding memory device in the first grouping arranged in a same column, and each memory device selectively provides either self-data retrieved from a constituent memory core or other-data retrieved from a memory core of another memory device during the read operation.

Memory modules with reduced rank loading and memory systems including same

An optical transmission converter comprises a wavelength selector configured to output a reception wavelength selection signal and a transmission wavelength selection signal in response to a wavelength control signal, an opto-electrical converter configured to convert a selection optical signal into a reception electrical signal based on a reception optical signal from a host device and the reception wavelength selection signal, and an electro-optical converter configured to convert a transmission electrical signal into a transmission optical signal based on the transmission wavelength selection signal and the transmission electrical signal.

Optical transmission converter, memory system comprising same, and related method of operation

A memory device is provided. The memory device includes programming first bit data into a plurality of memory cells; identifying target memory cells which are in a first state and whose threshold voltages are equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating a plurality of third bit data by performing a first process on the second bit data; selecting third bit data which changes a largest number of target memory cells from the first state to a second state in response to the memory cells being programmed with each of the plurality of third bit data from the plurality of third bit data; and programming the selected third bit data into the memory cells.

Memory device and method for driving the same

A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a buffer that inputs a first signal and outputs a first delay signal, a command decoder that outputs a second signal, a mask pulse signal generator that inputs the first delay signal and the second signal and generates a mask pulse signal, and a signal reshaper that inputs the first delay signal, the second signal and the mask pulse signal and reshapes the first delay signal or the second signal.

Semiconductor memory device with signal reshaping and method of operating the same

A clock generation device includes a flip-flop, a clock division unit, and a clock comparator. The flip-flop generates a chip selection signal synchronized with an internal clock signal. The clock division unit generates second divided clock signals based on a first divided clock signal. The clock comparator selects ones of the second divided clock signals based on the chip selection signal. The clock division unit divides the internal clock signal based on the first divided clock signal and the selected one of the second divided clock signals.

Divided clock generation device and divided clock generation method

A delay-locked loop circuit includes a phase detector and a coarse-lock detector. The phase detector receives a feedback clock and a first clock to generate first and second phase detecting signals, respectively. The coarse-lock detector generates a coarse-lock signal based on changes of phase of the first and second phase detecting signals.

Delay-locked loop circuit and method of controlling the same

A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and outputting a check signal indicating that the frequency of the input frequency signal is equal to or lower than a reference frequency when all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal, a delay lock reset unit generating a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform a delay lock process, and a direct phase detector controlling a coarse locking window on the basis of the check signal and generating a pair of phase detection signals indicating logic levels of the external clock. According to this configuration, since the coarse locking window is controlled as per a frequency band, it is possible to prevent a failure of a coarse locking and to achieve an improved circuit performance.

Delay locked loop circuit for preventing failure of coarse locking

A delay locked loop includes an auxiliary phase shifter for controlling a phase blending point after the delay locked loop is initially locked, thereby reducing jitter. A control circuit directs a phase blender to detect the point where two delayed signals are phase-blended, and directs the auxiliary phase shifter to select between a delayed clock signal and a received clock signal. When the point where the two delayed signals are phase-blended is in-between first edges of the two delayed signals, the control circuit directs the auxiliary phase shifter to transmit the received clock signal without delaying the clock signal. When the point where the two delayed signals are phase-blended is close to at least one of the first edges of the two delayed signals, the control circuit directs the auxiliary phase shifter to delay the clock signal by a predefined time. As a result, bang-bang jitter in the delay locked loop is reduced.

Delay locked loop having small jitter and jitter reducing method thereof

A delay-locked loop (DLL) includes a delay line and a control circuit. The delay line delays an input clock signal based on at least one phase control signal to generate an output clock signal. The at least one phase control signal indicates whether the output clock signal leads or lags the input clock signal. The control circuit generates a division control signal by determining whether the output clock signal is locked with respect to the input clock signal, and generates the at least one phase control signal based on the division control signal. Accordingly, a locking time and bang-bang jitter may be reduced.

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Seoul, South Korea

In-Dal Song